Table of Contents
Advertisement
CPU
2.6.
Bus Signals
Zilog
CPU
Table 2-6 lists the pin assignments for the ZBI backplane 95
pin Euro connector (PI).
Table 2-6.
ZBI Connector (PI) Pin Assignments
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
ROW A
SIGNAL
RESET-
CAI-
BAI-
MMAI-
IEI3
IEI2
IEI1
INTl-
R/W-
S2
SO
ME-
AD31
AD28
AD25
AD22
AD20
ADl7
ADl1
AD9
AD6
AD3
ADO
PWRBAD-
+5V
-5V
+12V
-12V
*
GND
ROW
B
SIGNAL
WAIT-
CAO-
BAO-
MMAO-
IE03
IE02
IE01
INT2-
B/W-
S3
Sl
AS-
STOP-
AD29
AD25
AD23
AD21
AD18
ADIS
AD12
ADIO
AD?
AD4
ADI
MCLK
+5V
-5V
+12V
-l2V
*
GND
ROW C
SIGNAL
CAVAIL
CPUREQ-
BUSREQ-
GND
MMREQ-
GND
INT3-
W/LW-
S4
GND
DS-
N/S-
GND
AD30
AD27
AD24
GND
AD19
AD16
AD13
GND
AD8
ADS
AD2
BCLK
+5V
-5V
+12V
-12V
*
GND
*
-12V is
allocated space on the ZBI backplane,
but
is
not
used
or
generated
by
the
System 8000.
12V is
presently only used for Memory.
2-5
Zilog
2-5
Advertisement
Table of Contents
