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CPU
6.·1.
General
Zi10g
SECTION 6
TIMING
CPU
The System 8000 CPU, through the Z800lA microprocessor, exe-
cutes
instructions
by
stepping through sequences of basic
machine cycles, memory read or write,
I/O
device
read
or
write,
interrupt
and segment trap request acknowledge, and
internal execution.
Each of
these
basic
cycles
requires
three
to
ten
clock
cycles to execute.
Instructions that
require more than ten clock cycles are divided into
several
machine
cycles.
No machine
~ycle
is longer than ten clock
cycles which provides a fast response to a Bus Request.
The following timing diagrams show the relative timing rela-
tionships
of
all the Z8001A CPU signals during each of the
basic operations.
When a machine cycle requires
additional
clock
cycles
for CPU internal operation, one to five clock
cycles are added.
Memory and I/O read and write, as well as
the interrupt acknowledge cycles, are extended by activating
the WAIT- input.
For exact timing information, refer to the
Memory Read and Write timing diagram.
The WAIT- input is asynchronous and the setup and hold times
for
WAIT- relative to the clock must be met.
The asynchro-
nous WAIT- signals generated, are synchronized with the
CPU
clock before transmission to the CPU.
6.2.
Memory Read and Write
Memory read and
instruction
fetch
cycles
are
identical,
except
for the status information on the STO - ST3 outputs.
During a memory read cycle, the segment number is output one
clock
cycle
earlier than the 16-bit address offset to com-
pensate for a delay in the memory management circuitry.
The
MMUs
on
memory access violation provide SEGT- trap request
input to the CPU that results in Segment Trap Acknowledge on
the status outputs and the Segment Trap Acknowledge Cycle.
A valid address is indicated
by
the
rising
edge
of
the
address
strobe.
Status
and mode information become valid
early
in
the
memory
access
cycle
and
remain
stable
throughout.
~-1
Z110g
6-1
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