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CPU
Zilog
CPU
3.4.7.4
Segment Trap: This trap
occurs
when
one
of
the
three
MMUs
detects
a
memory
access violation such as an
offset greater than
the
assigned
segment
length.
On
a
memory access violation, the MMU activates the Suppress line
used to inhibit memory requests. Segment
trap
remains
low
until
the CPU trap acknowledge signal is received.
When an
access violation occurs, Suppress is asserted for that cycle
and
all
subsequent
CPU memory references until the end of
the instruction.
The acknowledge cycle is
always
preceded
by an instruction fetch cycle that is aborted.
Following
the
acknowledge
cycle,
the
CPU
automatically
pushes the program status words and program counter onto the
system stack, and loads a new program status word
and
pro-
gram
counter.
The
segment
trap line is reset during the
acknowledge cycle and no suppress is
generated
during
the
stack push.
The segment trap also occurs on a write warning of
a
write
into
the
lowest
256
bytes of a stack.
This sets the SWW
flag but no segment
trap
request
is
generated.
Separate
hardware
on
the board detects and generates a segment trap
and suppress if memory reference is made to a system segment
while the CPU is in normal mode.
3.5.
Memory Management
The major functions of the memory management Z8010
MMUs
on
the System 8000 CPU board are:
1.
To provide flexible and efficient
allocation
of
main
memory
resources during the execution of the operating
system and user tasks.
2.
To support multiple independent tasks
that
can
share
access to common resources.
3.
To provide protection
from
unauthorized
or
uninten-
tional access to data or other memory resources.
4.
To detect obviously incorrect use of memory by an
exe-
cuting task.
5.
To partition main memory resources
and
separate
user
from system functions.
The three Z8010 MMUs are connected to the
Z8001A
CPU
with
special
logic that is used in one of the two following con-
figurations:
3-14
Zilog
3-14
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