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CPU
Zilog
CPU
agree with the system baud rate selection.
Switches 2 and 3
of
U70
are
used to select the primary boot device listing
for the SPUD Diagnostic.
When addressed by FFCl from the address generator (U24,sheet
12)
with
write
(IR/W-)
and
system
configuration
(SYS.
CONFIG-) lines both low, the SCR
register
(U36,sheet
14)
inputs
the
lower
nibble data bits ADINO through ADIN3 and
sets control bits DO - D3. The DO through
D3
control
bits
BDMEMON-,MMUONH, SEG USER, and CLR PARITY- respectively, are
part of the system configuration
control
of
the
separate
board functions. When the CPU reads the system configuration
from buffer (USl), the read (IW/R-) and SYS. CONFIG-
inputs
are
both
low
gating U22 and enabling the buffer US1.
The
upper nibble (ADIN4-ADIN7) is preset and
controled
by
the
baud rate selector switch (U70).
The onboard diagnostic monitor requires that before power-up
the
system console serial channel be set to the appropriate
baud rate (Figure 4-8).
ADINO-7
IRIW-
.---er~
I/O
ADO=} SYS.CONm-
GENERATOR
IWIIt --<L...~
o
p
ClI
. . . . . . . . . .
I ! ! ! ! ! ! !
c c c c c c c c
~
1
~
~
~
3
5
~
t
DO
01
D2
$V
uti
"".K
1'_'_
Figure 4-8
System Configuration Register (Sheet 14)
4-15
Zilog
4-15
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