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CPU
Zilog
I
IN11!RNA&. ADDReSS
DATA IUS AGO - AD11
VECTOR
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It...
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IORQ-
ZIOD1A
LOGIC
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HAND
ZI08
CPU
SHAKING
DmCE
IST3
LOGIC
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G2A
U4G,u.tt
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r~
U2I
U42
D-
CIii
U28
VI-
VECTORED IHTIIUlUPT
AEQUUT
I
Figure 4-5
vectored Interrupt
CPU
4.5.2.
Vectored Interrupt Daisy Chain:
The ZaOOlA CPU ack-
nowledges
the
peripheral
SIO,CTC, and PIO devices using a
device priority "daisy chain" scheme.
A vectored
interrupt
from
a
higher
priority
device in the chain automatically
disables interrupts from those of lower priority.
In
Sec-
tion 3, Table 3-4 lists the priority assigned to onboard and
offboard peripherals.
The interrupt "daisy chain'" has been -rmpl'emented bec-ause
of
the
large number of peripheral devices serviced both on and
off the CPU
board.
Each
Z80S
peripheral
device
has
a
separate
input and output line linked to the next device as
shown in Figure 4-5.
Both the Interrupt Enable In (IEI) and
the Interrupt Enable Out (IEO) signals are active high.
A logic "I" on the IEI input to a device means that no other
device of higher priority is being serviced by the
cpu.
The
IEO output signal is high only when ,the IEI input signal
is
high
and
the
CPU
is not servicing an interrupt from this
device. The IEO signal is connected to the IEI input of
the
next
lower
priority
device, and blocks the lower priority
devices from interrupting the CPU while
a
higher
priority
device is being serviced.
The order of priority is controlled by the
lEO
AND
gating
and
by
combining
U37
and
U38,
the
vectored
interrupt
accelerator, to produce the lEO signal block to the ZaI
bus
and the SIO 2,5IO 3, and PIO 0 IEI signals.
4-8
Zirog
4-8
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