Table of Contents
Advertisement
CPU
3.2.
Memory Addressing
Zilog
CPU
The address generated by the Z800lA CPU
is
always
a
byte
address.
However, the local memory addressing is organized
in lIS-bit words and the main
(offboard)
memory
in
32-bit
double
words.
All instructions and word operands are word
aligned and addressed by even addresses.
For all word tran-
sactions
with
memory,
therefore,
the
least
significant
address bit is zero.
For all memory byte transactions,
the
least
significant
address bit determines which byte of the
memory word is needed.
An even address specifies
the
most
significant
byte,
and an odd address the least significant
byte.
3.2.1.
Local Memory:
The local memory space
is
a
Kbytes
(4K words) of EPROM program memory and is organized as words
at locations 0 through lFFE
hexidecimal.
NOTE:
Refer
to
Appendix
A
for
substitute
16K
EPROM.
Also, 2 Kbytes of
read/write
memory
are
addressable
from
locations
2000
through
27FF
hexidecimal.
The RAM memory is both byte and
word addressable.
Onboard
memory
space
facilitates
the
power-up
bootstrapping of the operating system and provides
the hardware diagnostics.
It is entered on power-up or sys-
tem
reset
on
the logical memory bus of the zaOOlA CPU and
resides in segment zero.
3.2.2.
SCR Memory
Selection:
The
board
hardware
System
Configuration Register (SCR) is a programmable a-bit (DO-D7)
input/output port with a 4-bit (D4-D7) upper read/only
nib-
ble
configured
by
a four bit dip switch (U70) for console
baud rate.
The lower four bits (DO-D3) provide
the
CPU
with
onboard
memory,
MMU,
segmented
user~
and
ECC Error NMI enabling
functions.
The 00-03 bits are cleared (logic 0)
on
system
RESET
to
initialize the system: Onboard memory is enabled,
MMUS are disabled, nonsegmented user enabled, and ECC
Error
cleared.
As long as board memory enable bit DO of the
SCR
is
reset
(logical
0) ,the total local memory space 0 through 27FF hex
overlays the segment 0 main memory space 0 through 27FF.
At
power-up
or system reset time, the SCR DO bit is cleared to
logic 0 and enables the local memory.
Writing a logic
1
to
bi t
DO
of
theSCR
disables
"onboardmemory and maps all
memory references to offboard main memory.
The contents
in
local RAM are not lost.
3-3
Zilog
3-3
Advertisement
Table of Contents
