Peripheral Interrupt Timing; Peripheral Handshaking Logic; Bus Request Acknowledge Cycle - ZiLOG System 8000 Hardware Reference Manual

CPU Zilog
CPU
6.4.2. Bus Request Acknowledge Timing: A low on the
BUSREQ- input indicates to the CPU that another device is
requesting the Address/Data and Control buses. The asynchro-
nous BUSREQ- input is synchronized at the beginning of any
machine cycle. If BUSREQ- is low, an internal synchronous
BUSREQ- signal is generated, which afer completion of the
current machine cycle ,
causes_th~_BUSACK-
output to go low
and- all bus outputs to go into the high impedance state. The
requesting device can then control the bus. When BUSREQ- is
released, it is synchronized with the rising clock edge and
the BUSACR- output goes high one clock period later, indi-
cating the CPU will again take control of the bus.
i i i i i & . i i . - - - - - - - l - \
aT.......
...........
_-----......,
AI
•
_ - -__ AY. . . . .- - -
Figure 6-5 Bus Request Acknowledge Cycle
6.5. peripheral Interrupt Timing
The peripheral interrupt requires handshaking logic and
software to make the Z808 peripherals compatible with the
Z8001A. The Z808 peripherals request a vectored interrupt by
pulling the VI- input of the CPU low. The CPU samples this
input at a specified time prior to the end of any instruc-
tion execution and acknowledges the interrupt with a
specific status code VIACK-o The VIACK- input to the Z80
peripheral handshaking logic acknowledges interrupts by gat-
ing the combination of control signals IORQ- and Ml- both
active. Potential conflicts between overlapping interrupt
requests are resolved with a daisy-chain arrangement between
the lEO outputs and lEI inputs of the peripheral components.
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Zilog
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