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Desktop
System 8000
Hardware reference manual
ZiLOG System 8000 Hardware Reference Manual
Central processing unit
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Also See for System 8000
:
Hardware reference manual
(366 pages)
,
User manual
(65 pages)
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Contents
Table of Contents
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Table of Contents
Table of Contents
Overview
1 Description
Serial and Parallel I/O
CPU Functional Diagram
Memory and Memory Management
Specifications
Introduction
Electrical Specifications
Physical Specifications
Environmental Specifications
Electrical Requirements, Domestic
Physical Specification
CPU I/O Connector
96 Pin Euro Standard Connector
CPU Pin Assignments (P2)
CPU I/O Bus, Signal Definitions
Bus Signals
ZBI Connector (PI) Pin Assignments
ZBI Signal Definitions
ZBI Status Lines
Data Width Codes
Status Transaction Coding
Jumper Selection
Line Printer Jumper Selection
Data Width: Byte, Word, Long Word
Baud Rate Selection
Baud Rate Setting and
Functional Description
Description
Z8001A CPU Memory Addressing
Z8010A Memory Management Units
Memory Addressing
Local Memory
SCR Memory Selection
Main Memory
Byte Transactions
I/O Addressing
Memory Management
I/O Address,Device and Channel
Special I/O MMU Address
NMI Identification
Peripheral Device Priority
Peripheral Interrupt Priority
Clock Generation
Baud Clock
Real Time Clock
Clock Generation Circuit
Baud Clock Generator
Parallel I/O Ports
Printer Control Outputs
Printer Status Inputs
Serial Input/ Output
Printer Control Signals
Printer Status Signals
Serial I/O with CTC Channels
4 Interrupts
Vectored Interrupt
Vectored Interrupt Daisy Chain
NMI Identification
Interrupt Priority Connection
System Reset Logic
Memory Addressing
Byte Transactions
Read-Only Memory
Read/Write Memory
Byte Swap Buffer
Memory Management Control Logic
Non-Segmented Operating System
Non-Segmented User Program
Segmented User Program
MMU Configuration
System Configuration Register
System Configuration Register
SCR Configuration
Segmented/Non-Segmented User
Setting Console Baud Rate
Parity Error Checking
Special Logic Circuits
External Violation Registers
Address/Data Buffers and Steering Logic
Peripheral Handshaking Logic
T3 Wait State Generator Logic
Maintenance
General
Preventive Maintenance
System Power-Up Diagnostics
SPUD Diagnostic Error List
Inspection and Replacement
Section 6 Timing
General
Memory Read and Write
Memory Read and Write Timing
Input/Output Timing
Interrupt Operation
Write Cycle
Read Cycle
Status Saving Sequence
Segment Trap/Interrupt Acknowledge Cycle
Peripheral Interrupt Timing
Peripheral Handshaking Logic
Bus Request Acknowledge Cycle
Return from Interrupt
Interrupt Acknowledge Cycle
Return from Interrupt Cycle
Appendix A 16 Kilobyte Eprom Memory
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See also:
User Manual
,
Hardware Reference Manual
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System 8000™
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