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Z8 Encore!
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ZiLOG Z8 Technical Manual
Microcomputer
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User manual
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User manual
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Contents
Table of Contents
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Table of Contents
Table of Contents
Table of Contents (Continued)
Chapter 1 . Zbfamily Overview
Introduction
Nstruction Set
Architecture
Development Device (Z8612)
Protopack Emulator (Z8603/13)
Basic/Debug Interpreter (Z8671)
Applications
Chapter 2. Architectural Overview
Introduction
Address Spaces
Figure 2-1 Z8 Block Diagram
Register File
Register Pointer
Instruction Set
Data Types
Addressing Modes
I/O Operations
Timers
Interrupts
Figure 2-2 Bits in Register
Oscillator
Protopack
Chapter 3 . Addressspaces
Introduction
Figure 3-1 Register File
Error Conditions
Figure 3-4 Working Register Addressing
CPU Control and Peripheral Registers
CPU Program Memory
Figure 3-5D Z8682 Program Memory Map
CPU Data Memory
CPU Stacks
Figure 3-7 Stack Pointer
Chapter 4 . Addresshodes
Introduction
Register Addressing (R)
Indirect Register Addressing (IR)
Indexed Addressing (X)
Direct Addressing (DA)
Relative Addressing (RA)
Figure 4-5 Indexed Addressing
Figure 4-6 Direct Addressing
Figure 4-7 Relative Addressing
Immediate Data Addressing (1M)
Figure 4-8 Immediate Data Addressing
Chapter 5. Instruction Set
Functional Summary
Processor Flags
Carry Flag (C)
Zero Flag (Z)
Sign Flag (S)
Overflow Flag (V)
Decimal-Adjust Flag (D)
Half-Carry Flag (H)
Condition Codes
Notation and Binary Encoding
Assembly Language Syntax
Condition Codes and Flag Settings
Instruction Descriptions and Formats
Figure 6-2 Z8601/11 Pin Assignments
Chapter 6 . External Interface (Z8601, Z8611)
Data Memory
Bus Operation
Figure 6-4 Ports 0 and 1 Stack Selection
Figure 6-5 Data Memory Operation
Address Strobe (AS)
Data Strobe (DS)
External Memory Operations
Shared Bus
Figure 6-6B External Memory Write Cycle
Figure 6-7 Shared Bus Operation
Extended Bus Timing
Figure 6-8 Extended Bus Timing
Figure 6-9A Extended External Instruction Fetch, or Memory Read Cycle
Instruction Timing
Figure 6-11 Instruction Cycle Timing (One Byte Instructions)
Reset Conditions
Figure 6-13 Ports 0 and 1 Reset
Chapter 7 . External Interface (Z8681, Z8682)
Introduction
Pin Descriptions
Figure 7-1 Z8681/82 Pin Functions
Configuring Port
Z8682 Initialization
Read/Write Operations
External Stacks
Data Memory
Figure 7-6 Z8682 Port 0 Memory Operation
Bus Operation
Address Strobe (AS)
Data Strobe (OS)
Extended Bus Timing
Instruction Timing
Z8681 Reset Conditions
Z8682 Reset Conditions
Chapter 8 . Resetand Clock
Reset
Clock
Test Mode
Figure 8-6 Battery-Backed Register Supply
Interrupt Testing
Romless Operation
Chapter 9 Port
Figure 9-1 I/O Port and Port Mode Registers
Read/Write Operations
Handshake Operation
Figure 9-3 Port 0 I/O Operation
Figure 9-4 Port 0 Handshake Operation
Introduction
Mode Registers
Input and Output Registers
Port 1
Read/Write Operations
Figure 9-5 Port
Figure 9-6 Port 1 I/O Operation
Figure 9-8 Port
Figure 9-11 Port
Special Functions
Port Handshake
Figure 9-15 Z8 Input Handshake
I/O Port Reset Conditions
Figure 9-17 Input Strobed Handshake Using Port
Figure 9-20 Z8681 Ports 0 and 1 Reset
Figure 9-21 Z8682 Ports 0 and 1 Reset
Figure 9-22 Port 2 Reset
Chapter 10. Interrupts
Introduction
Interrupt Sources
External Interrupt Sources
Figure 10-1 Interrupt Control Registers
Internal Interrupt Sources
Interrupt Initialization
Figure 10-5 IRQ Register Logic
Figure 10-7 Interrupt Priority Register
Interrupt Mask Register Initialization
IRQ Software Interrupt Generation
Figure 10-8 Interrupt Mask Register
Figure 10-9 Interrupt Request Register
Vectored Processing
Nesting of Vectored Interrupts
Figure
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See also:
User Manual
Z8 Microcomputer
Technical Manual
April 1983
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