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CPU
Zilog
CPU
Each channel has an independently programmed selectable baud
rate from 300 Hz up to 19.2 KHz for individual terminals and
supplied by three Z80B Counter Timer
Circuits(CTCs).
Each
channel
is
limited to the same baud rate for receiving and
transmitting.
The CTCs are driven by a baud rate oscillator
which
is
independent
of
the
system
clock frequency.
A
daisy-chain peripheral device priority
scheme
selects
the
highest priority onboard and offboard peripheral device.
Plug P2/J2l supplies the
I/O
connection
to
the
offboard
peripheral
equipment.
Either a Centronics or Data Products
interface for a line printer is established
by
two
jumper
changes on the board.
1.3.
Memory and Memory Management
The local onboard
memory
is
used
for
bootstrapping
the
operating
system and for hardware diagnostics.
It consists
of 8K bytes (4K words)
of
resident
Erasable
programmable
Read-Only'Memory(EPROM)
and
2K bytes (lK words) of Random
Access Memory(RAM) •
NOTE: The 8K EPROM has been increased to l6Kbytes
as
shown
by the Logic Drawing (Appendix B)
(DZ-0288).
Three Zilog Z80l0A Memory Management Units (MMUs) facilitate
an
efficient
and
flexible
usage
of
the
System 8000 by
dynamic relocation of tasks in main memory.
Special control
logic
is
implemented
that supports all the major goals of
memory management (Para.3.5). For the nonsegmented operating
system,
the
three
MMUS
separate
code(program) ,data, and
stack areas, and the operating system uses segment 0 of each
of
the
three MMUs for its code, data and stack space.
The
data and stack MMUs are selected by special hardware on
the
board that compares the logical address with the contents of
a hardware
system
break
register
to
determine
the
MMU
selected.
The MMU N/S- input selects the MMU.
The non-segmented user programs are run in any
segment
(2-
63) while segmented user processes can use one or more logi-
cal segments (2-63) to (66-127).
The SEG USER
bit
of
the
System
Configuration
Register must be set before running a
segmented user process. The normal break
register
replaces
the
system
break register and the NORMAL MMU input selects
the MMU. This configuration reflects a non-segmented operat-
ing system for the segmentedornon-segmehted user.
1-5
Zilog
1-5
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