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CPU
Zilog
CPU
For a translated physical address (TRAD 8-23) from the MMUS,
the
bus
address buffers (Ul14,Ul17) are enabled and output
AD8-AD23 to the ZBI. The
low
order
byte
(LAD
0-7)
from
address buffer(U1l0)
is placed on the ZSI (ADO-AD7)
•
For a nontranslated address
of
main
memory,
the .logical
address
(LAD
8-15)
and segment (ISNADO-6) are directed to
address buffers (Ul15,Ul16) and placed on the ZBI
(AD8-23).
The
offset
low
order
byte (LAD 0-7)
is gated at the same
time.
The address buffers are disabled and
data
buffers
enabled
during
the offboard write or read data cycle.
The bidirec-
tional data buffers (U111,U113)
(sheet 13) are controlled by
the
Write/Read
and
data
strobe
signals (IW/R-, IDS, and
IDS-) and the bus acknowledge signal (Z
BUS
ACK-).
For
a
write
data cycle, IW/R- is high and
IDS~
is low at the gate
U15 setting the write on the data buffers. The IDS high sig-
nal gates U21, U31,and enables a write to the ZBI.
For a data word read, IW/R- and IDS- are both low at U15 and
the
resulting
high
is inverted and sets the read input of
both data buffers. The data strobe (IDS) strobes the
l6-bit
data word.
For
a
byte
read
of
an
even
address,
the
byte
swap
buffer(Ul12)
is enabled from the byte swap logic on the low
byte by LADO.
The ENABLE
BYTE
SWAP
signal
generated
is
gated (U31) with the READ DATA STROBE from U15 to enable the
byte swap buffer. The ENABLE BYTE SWAP- low signal
disables
U111 and Ul13 and the low byte from the ZBI becomes the high
byte -(IAD8-15) on the CPU data bus.
4.10.3.
T2, T3 Wait State Generator
Logic:
On
boot?trap-
ping
the
system,
references
to
local
memory requlre an
automatic one wait state insertion.
This wait state is pro-
vided
by U28 (sheet 14).
The T2 WAIT- is activated for one
CPU clock cycle during T2 clock period.
When necessary, the WAIT line is called
upon
to
extend
a
transaction
for
I/O or memory if the device (or memory)
is
not ready or fast enough to keep up with the processor.
If
BUS
WAIT is
active in the middle of the T3 clock cycle, an
additional wait state T3 is generated.
This
wait
is
sup-
pI ied
by
the fl i p-flop (U97)
(Figure 4-9) which inserts an
additional clock period by holding the CPU clock at
a
high
level for one clock cycle, (TW).
4-18
Zilog
4-18
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