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CPU
Zilog
Table 5-1. SPUD Diagnostic Error List
CPU
ERROR
PI
P2
P3
P4
CURS
*
DESCRIPTION
#
PRINTED
0000
P
No External Memory*·
0001
SEQ #
ADDR
RD
0
Seg. Addr Fault
**
0100
SEQ #
ADDR
TO
RD
W
Mem. Addr Fault
0101
SEQ #
ADDR
TO
RD
Data Line Fault
0102
SEQ #
ADDR
TO
RD
'As'
Data Fault
0103
SEQ #
ADDR
TO
RD
'55' Data Fault
0104
No Good Segments Above Zero··
0100
SEQ #
ADDR
TO
RD
E
Segment Zero Memory Test
0101
SEQ #
ADDR
TO
RD
(Descriptions
As
Above)
0102
SEQ #
ADDR
TO
RD
0103
SEQ #
ADDR
TO
RD
0200
R (sp)
ECC Single-bit Correction Failure
0201
U
ECC two-bit trap failure
0202
P (sp)
ECC two-bit error not reported
0203
SEQ #
ADDR
ECC Check Byte RAM error
0300
MMU
SDR
TO
RD
D
MMU's Not Individually Ad-
dressable
PORT I
FIELD #
0301
MMU
SOR
TO
RD
SAR or DSCR Indexing Fault
PORT #
FIELD #
0302
MMU
SOR
TO
RD
SOR
'As'
or '55' Data Fault
PORT #
FIELD #
0303
MMU
TO
RD
MMU Control Register
'As'
or
'55' Fault
CMD#
0304
REG I
TO
RD
System/Normal Break Register
'As'
or
'5$'
Fault
0305
MMU
SOR#
VDAT
I
Stack MMU Did Not Trap On
WI
Limit Test
030S
A
Unexpected Trap
0305
Q
Unexpected Trap
030S •
N
Data MMU Did Not Trap On
Limit Test
0305
0
Stack MMU Did Not Trap On
Read-Only Test
0305
S
Data MMU Did Not Trap On
Read-Only Test
0306
MMU
SDR#
TO
RD
T
Translation Fault On Data MMU
Port
I
0307
MMU
SOR#
VDAT
Unexpected Trap
PORT #
0308
MMU
SORI
TO
RD
I
Translation Fault On Stack MMU
PORT
I
0309
MMU
SOR#
VDAT
Unexpected Trap
PORT
I
0310
MMU
SOR#
TO
RD
C
Translation Fault On Code
~ru
PORT I
0311
MMU
SORI
VDAT
Unexpected Trap
PORT #
0312
MMU
SORI
S (sp)
No Trap On Code MMU Limit
PORT
I
Test
5-3
Zilog
5-3
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