Table of Contents
Advertisement
CPU
2ilog
CPU
violation to the CPU and no MMU selected.
4.8.1.
Non-segmented Operating System:
For a non-segmented
operating
system,
the
segment
descriptor
register (SDR)
number
0
is used in each
of
the
memory
management
units
(MMUs) •
The
MMUs
Ml,M2,and
M3
are identified for code,
data, and stack areas respectively.
Ml
translates
program
memory references while M2 and M3 translate all other memory
references.
The selection of M2 or M3 is by a comparison
of
the
upper
byte
of
the
16-bit logical offset and the contents of the
system break register(SBR) programmed at the FFC9 address of
the
I/O
address generator (U24).
The SBR (U?2,sheet 10) is
a
program
addressable
hardware
register
that
inputs
the programmable address byte to
the
comparator
(US2,
US3).
When
compared
with
the
logical
address
upper
byte
(LAD 8 - LAD
15),
logical values lower
than what is contained in the
register
produce
an
active
DATA
REF
output. The output is then gated and produces the
MDATA- input to the Data MMU M2.
If
after
comparison
the
logical
values
are greater than or equal to the SBR value,
an inactive DATA REF is produced and activates
the
MSTACK-
input of the stack MMU M3 (U86).
The memory management control
logic
produces
the
MCODE-,
MDATA,
and
MSTACK-
signals
to
the Normal/System- (N/S-)
inputs of each of the three Code, Data, and Stack
MMUs
for
MMU
selection.
When
the N/S- line matches the Normal Mode
Select (NMS) flag within the MMU, the
MMU
is
enabled
and
address translation
performed=
Logical addresses with values lower than the SBR are treated
as
data addresses and directed to the data MMU M2.
Logical
addresses equal to or greater than the SBR
are
treated
as
stack addresses and directed to the stack MMU M3.
4.8.2.
Non-segmented User
Program:
A
non-segmented
user
program runs in segment 63 using segment descriptor register
63 in Ml,M2, and M3 to provide the separate code, data,
and
stack areas.
The normal break register (NBR)
(U?l)
replaces
the SBR for the user program. The logical address comparison
and MMU selection
far
user is the same however, the address-
ing of theNBR
is Ftbl.
4-13
2110g
4-13
Advertisement
Table of Contents
