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CPU
Zilog
CPU
The Z8010A Memory Management
Units
transform
the
logical
address
output of the ZaOOI CPU, comprised of concatenation
of the segment and offset, into a 24-bit physical address.
The ZaODIA CPU outputs status information from
four
status
lines
(STO-ST3)
and
distinguishes between system mode and
normal mode memory references by a status flag (N/S-).
The
status
conditions
are
mutually
exclusive
and encoded to
extend the addressing range or protect accesses
to
certain
portions of memory.
For each access to memory, the external
circuit checks whether the CPU status is appropriate for the
memory reference.
The ZaOOIA CPU can run in one of two modes: System
or
Nor-
mal.
In
the
System
mode, all of the instructions can be
executed and all of the CPU registers can be accessed.
This
mode
is
is
used for programs of the operating system.
In
normal mode, certain instructions including all I/O instruc-
tions
are
not
executable.
Also, the control registers of
the CPU are inaccessible.
User programs are run
in
normal
mode.
The two running modes of the ZaOOIA CPU each have a copy
of
the
stack
pointer,
one
for system mode and the other for
normal mode. Two sets
of
stack
pointers
facilitate
task
switching
when interrupts or traps occur.
The normal stack
never contains system information.
The
Memory
Management
Units
(MMUs)
use
the
NORMAL/SYSTEM (N/S-)
input to select the appropriate MMU for
memory management.
3.1.2.
Z8010A Memory Management units:
The three MMUs sup-
port separate translation tables for each Za001A CPU address
space.
Each of the ZaOIOA 64 variable sized
segments
(256
to
fi4
Kbytes)
can be mapped into a total physical address
space of 16 Mbytes.
All 64 segments are
randomly
accessi-
ble.
Each MMU uses a translation table to
transform
the
23-bit
logical
memory
address
output
from the ZaOOIA CPU into a
24-bit physical memory address which
becomes
the
buffered
output
to
the
ZBI
bus and memory controller.
Three MMUs
allow separation of code, data, and stack references.
Each
memory
management
unit can translate addresses for 64 seg-
ments.
The memory management units are enabled
by
the
D1
(MMU
ONH)
bit
within
the programmable hardware a-bit I/O
port System Configuration Register (SCR) described in
para-
graphs 3.2.2 and 3.2.3.
3-2
Zilog
3-2
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