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CPU
Zilog
CPU
3.5.1.3
Segmented User Program: A
segmented
user
program
uses M2 and M3 for an address space consisting of 124 or 128
segments, again without separating
code,
data,
and
stack
areas.
For the non- segmented operating system, the segment
numbers 0, 1, 64, and 1j5 are reserved since it requires
the
SDR
°
and 1 of M2 and M3.
Refer to paragraph 3.5.2.
3.5.1.4
Jumper Configuration: The system segmented/ nonseg-
mented
operation is by hardware jumpers on the board and by
the operating system software.
The hardware jumpers config-
ure the MMU control logic for a non-segmented operating sys-
tem when shipped. These jumpers are not to be changed in the
field.
The hardware jumper connections are given in
the
Installa-
tion and Operation section.
3.5.1.5
Break Registers:
For
the
nonsegmented
operating
system
and
User,
two a-bit hardware registers, the System
Break Register (SBR) and the Normal
Break
Register
(NBR),
are
accessable
as input/output ports on the CPU board, and
assist the Memory Management sUbsystem.
During
any
memory
reference,
the
16-bit
logical address offset generated by
the CPU is compared to a break value given by
the
contents
of either the SBR or the NBR.
The SBR is referenced for the
break value if the segment number is zero, one, 64,
or
65;
otherwise, the NBR is referenced.
3.5.1.6
System Segments and Protection: The processor logic
partitions
the segments into system segments, (logical seg-
ments 0, 1, 64, and 65) and user segments, (logical segments
2
through
63 and 66 through 127).
A
reference to a system
segment always enables an SBR for comparison with the
logi-
cal
address
offset.
A reference to a user segment always
enables the
NBR.
These
comparisons
are
independent
of
whether the CPU is executing in system mode or normal mode.
The system segment detection
logic
prohibits
normal
mode
programs
from
accessing system mode segments.
Normal mode
references to system segments are not allowed and result
in
no
MMU
being
selected
and a segment trap forced upon the
CPU.
This violation is maintained until cleared by the seg-
ment trap acknowledge status of the CPU.
The MMU also generates a segment trap
when
it
detects
an
access
violation
or a write warning condition. In the case
of an access violation, the MMU activates a Suppress used to
inhibit
memory access. Segment traps to the CPU are handled
3-16
Zilog
3-16
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