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CPU
2110g
CPU
data byte
(ADO-AD7)
is
placed
on
the
high
order
even
half (IAD8-IAD15) of the CPU data bus.
4.6.1.
Byte
Transactions:
For
the
least
significant
byte/read
transaction
to
be
executed
by
the
CPU,
the
Byte/Word (B/W-) and Read/Write- (R/W-) output
signals
are
both
high
and
with
buffers (Ulll and Ul13) enabled, both
halves of the address/data bus are then read by the CPU.
For an offboard byte read transaction between
the
CPU
and
memory,
the
address/data
bit
(ADO) when high enables the
byte swap buffer (UI12) and disables the buffers
(UIII
and
Ul13)
putting
the
low data byte on the upper even half
of
the board data bus. The CPU reads the appropriate byte
from
the data bus.
4.6.2.
Read-Only Memory:
The local read-only memory
space
consists
of
four
(2k
x
8)
EPROMS
(U74-U77)
(8 Kbytes)
addressed at locations
a
through
IFFE
hexidecimal~
(See
Appendix for Model 10/11 and Models 21 and 31 applications.)
Each pair of EPROMS store the low and
high
bytes
of
each
word.
Since
the
CPU
always
reads full words from local
memory, the least significant address bit (ADO) is not
used
in
address
decoding.
The EPROMS are addressed by latched
addresses LADI through LADll.
When the internal memory request(IMEM REQ-) and board memory
on
(BD MEM ON-) signals are received
at the onboard memory
address decoder (USS), logic addresses
(LAD
12,13,14)
and
the ANDED LAD14 and
LAD 15 are input and decoded to produce
the signals for the onboard memory select logic
(sheet
10)
that separates the EPROM and RAM areas.
The one-of-eight memory address decoder selects between
the
EPROM
high
and
low byte pairs by gating (US6) the decoder
output signals (BDMEMA2K-,BDMEMB2K-) with IW/R-, all signals
active
low.
The
decoder
output
(BDMEMC2K-) enables the
onboard RAM as part of the
onboard
memory
select
circuit
(sheet 9) •
4.6.3.
Read/Write Memory:
The local read/write 2Kbyte
RAM
memory consists of four 2114 RAMs (US7-U60).
The gating of the LAD 0, IR/W-, IW/B-, and BDMEMC2K- signals
(logic
diagram
sheet 9) by the onboard memory select logic
(U54 and US6) creates the MEMC2KLO-
low
byte
chip
select
input
at
RAMS
US7
and
US8 and the MEMC2KHI- signal chip
select high byte input to RAMS US9 and U60.
When LAD
a
is
4-11
Zilog
4-11
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