Received Dsc (Wr2) Signal Route - Furuno FS-1575 Service Manual

3.3 Received DSC (WR2) signal route

The 36-kHz IF RX signal outputted from the WR2 board is converted to a digital signal
through the ADC and outputted to the FPGA. The FPGA retrieves DSC-band signals
necessary for the IF AGC control and band-pass filters and outputs these signals to the
DSP.
The DSP conducts signal processing, such as demodulation and symbol-by-symbol
demodulation, and transmits data to the main CPU. The main CPU analyzes the data
(MSG. data) and transmits the analyzed data to the FPGA.
The FPGA converts the data into a format that allows communication with the control
unit and transmits the converted data to the control unit. The control unit displays the
data as a DSC message.
DSC (WR2)
36kHz WR2 IF
U4
WR2
CODEC
RS-485 Serial data
From Controller
Fig. 7.6.12 Overview Diagram of WR2 Signal Channel
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T-CPU
U18 U11
FPGA DSP
C-IF C-CPU
U2 U10 U12
FPGA C-CPU
I/F
7-62
MOT
U19
U18 U29
MAIN
FPGA I/F
CPU
Display
7.6 T-CPU
RS-485 Serial data
To Controller