Transmitted Dsc Signal Route; Received Dsc (Wr1) Signal Route - Furuno FS-1575 Service Manual

3.1 Transmitted DSC signal route

The DSC MSG. data created by the control unit is transmitted to the transceiver unit in a
serial data format. This serial data is transmitted to the main CPU through the FPGA of
the T-CPU board. The main CPU generates a DSC signal and outputs it to the DSP. The
DSP modulates the signal by the FSK method and transmits the modulated signal to the
CODEC through the FPGA. The CODEC converts the data to a 36-kHz IF TX analog
signal and outputs it to the TX board.
TX: DSC
MSG. KEY-IN
MOT
RS-485 Serial data
U29
I/F
From Controller
Fig. 7.6.10 Overview Diagram of Transmitted DSC Signal Channel

3.2 Received DSC (WR1) signal route

The 36-kHz IF RX signal outputted from the WR1 board is converted to a digital signal
through the ADC and outputted to the FPGA. The FPGA retrieves DSC-band signals
necessary for the IF AGC control and band-pass filters and outputs these signals to the
DSP.
The DSP conducts signal processing, such as demodulation and symbol-by-symbol
demodulation, and transmits data to the main CPU. The main CPU analyzes the data
(MSG. data) and transmits the analyzed data to the FPGA.
The FPGA converts the data into a format that allows communication with the control
unit and transmits the converted data to the control unit. The control unit displays the
data as a DSC message.
DSC (WR1)
36kHz RX IF
U10
WR1
ADC
RS-485 Serial data
From Controller
Fig. 7.6.11 Overview Diagram of WR1 IF Signal Channel
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It is strictly prohibited to reproduce the document in whole or in part without prior written permission of FURUNO.
C-CPU
U3 U10
C-CPU FPGA
T-CPU
U29
U18 U11
MAIN
FPGA DSP
CPU
T-CPU
U18 U11
FPGA DSP
C-IF C-CPU
U2 U10 U12
I/F FPGA C-CPU
7-61
C-IF
RS-485 Serial data
U2
I/F
To Transciver
36kHz IF TX
U18 U4
FPGA CODEC
U19
U18
MAIN
FPGA
CPU
Display
7.6 T-CPU
TX
MOT
RS-485 Serial data
U29
I/F
To Controller