Verification Of Model: Board Inst Signal - Furuno FS-1575 Service Manual

Board Name
TX: 05P0856
DRV: 05P0866A, B
PA: 05P0867A, B
PA: 05P0868
COMB: 05P0869
TX FIL: 05P0870A, B
TX FIL: 05P0876
PA-IF: 05P0864
PA-IF: 05P0864A
RX: 05P0842
DUP-FIL: 05P0863
RX-FIL: 05P0862A, B
T-CPU: 05P0859
Note) INST signal is outputted from the WR1, WR2, COMB, and DUP FIL boards.

3. Verification of model: Board INST signal

The INST signal is used to verify whether or not the WR1, WR2, DUP FIL, and COMB
boards are mounted.
This signal not only verifies the model of a system in use, but also performs operation
that matches the specification of the system.
The INST signal is loaded by T-CPU when turning ON the power supply.
Like the hardware versions, the model of a system is detected by pulling up or down the
INST signal line on the relevant board side.
T-CPU
Use of INST signal
1) WR1 board: WR1 INST N
This signal is not in use.
CONFIDENTIAL (internal use only)
This confidential document is used only by FURUNO authorized persons.
It is strictly prohibited to reproduce the document in whole or in part without prior written permission of FURUNO.
Table 6.5.2 List of HW VER Verification Bits
Number of
Board Name
Bits
2 T-IF: 05P0861
1 T-IF: 05P0861A
1 MOT: 05P0860
1 WR1, 2: 05P0847A, B
1: INST PWR: 05P0874
1 SW REG: 05P0873
1 FET: 05P0872
2 (H, H) P-SW: 05P0871
2 (L, L) PANNEL: 05P0884
2 C-IF: 05P0853
1: INST C-CPU: 05P0852
2 COUP: 05P0875
2
MOT
xx INST_N
CPLD
Fig. 6.5.2 INST Signal
6-28
6.5 SERVICE: TEST
Number of Bits
2
2
2
2
1: INST
−
−
−
−
2
3
3
−
WR1
WR2
DUP-FIL
COMB