Transmitted Nbdp Signal Route; Received Nbdp Signal Route - Furuno FS-1575 Service Manual

2.1 Transmitted NBDP signal route

A NBDP message created by the NBDP terminal is transmitted to the transceiver unit in
a serial data format. This serial data is transmitted to the 78k CPU through the FPGA of
the T-CPU board. The 78k CPU generates a NBDP signal and outputs it to the DSP. The
DSP modulates the signal by the FSK method and transmits the modulated signal to the
FPGA. The FPGA serves as an interface between the DSP and the subsequent CODEC.
The CODEC converts the data to a 36-kHz IF TX analog signal and outputs it to the TX
board.
TX: NBDP
C-IF
From Terminal
U11
I/F
MSG. data
MOT
RS-485 Serial data
U29
I/F
From Controller
Fig. 7.6.8 Overview Diagram of Transmitted NBDP Signal Channel

2.2 Received NBDP signal route

The 36-kHz IF RX signal outputted from the RX board is converted to a digital signal
through the ADC and outputted to the FPGA. The FPGA retrieves NBDP-band signals
necessary for the IF AGC control and band-pass filters and outputs these signals to the
DSP.
The DSP conducts signal processing, such as demodulation and symbol-by-symbol
demodulation, and transmits data to the 78k CPU. The 78k CPU analyzes the data (MSG.
data) and transmits the analyzed data to the FPGA.
The FPGA converts the data into a format that allows communication with the control
unit and transmits the converted data to the control unit. The control unit transmits the
data to the NBDP terminal, and the terminal displays it as a NBDP message.
NBDP
36kHz IF RX
RX
RS-485 Serial data
From Controller
Fig. 7.6.9 Overview Diagram of NBDP RX IF Signal Channel
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C-CPU
C-IF
U10 U2
I/F
FPGA
T-CPU
U28
U18 U11
78k
FPGA DSP
CPU
T-CPU
U10 U18 U11
ADC FPGA DSP
C-IF C-CPU
U2 U10 U11
I/F FPGA I/F
7-60
RS-485 Serial data
To Transciver
36kHz TX IF
U18 U4
FPGA CODEC
MOT
U28
U18
78k
FPGA
CPU
Terminal
MSG.data
7.6 T-CPU
TX
RS-485 Serial data
U29
I/F
To Controller