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decremented from a positive number or zero to a
negative number. The request is preserved and
remains pending in the CPU until it is cleared. The
pending request is cleared when it causes an
interruption and by program reset.
The interval-timer condition is indicated by
setting bit 8 in the interruption code to one and by
setting bits 0-7 to zeros. Bits 9-15 are zeros unless
set to ones for other conditions that are
concurrently indicated.
The subclass-mask bit is in bit position 24 of
control register O. This bit is initialized to one.
Input/Output Interruption
The input/output (I/O) interruption provides a
means by which the CPU responds to conditions in
I/O devices and channels.
A request for an I/O interruption may occur at
any time, and more than one request may occur at
the same time. The requests are preserved and
remain pending in channels or devices until
accepted by the CPU. The I/O interruption occurs
at the completion of a unit of operation. Priority is
established among requests so that only one
interruption request is processed at a time. For
more details, see the section "Input/Output
Interruptions" in Chapter 12, "Input/Output
Operations. "
When the CPU becomes enabled for I/O
interruptions and a channel has established priority
for a pending I/O-interruption condition, the
interruption occurs at the completion of the
instruction execution or interruption that causes the
enabling.
An I/O interruption causes the old PSW to be
stored at location 56, a channel status word to be
stored at location 64, and a new PSW to be fetched
from location 120. Upon detection of equipment
errors, additional information may be stored in the
form of a limited channel logout at location 176.
When the old PSW specifies the EC mode, the
I/O address identifying the channel and device
causing the interruption is stored at locations
186-187, and zeros are stored at location 185.
When the old PSW specifies the BC mode, the
interruption code in PSW bit positions 16-31
contains the I/O address, and the
instruction-length code in the PSW is
unpredictable.
An I/O interruption can occur only while the
CPU is enabled for interruption by the channel
presenting the request. Mask bits in the PSW and
channel masks in control register 2 determine
whether the CPU is enabled for interruption by a
channel; the method of control depends on whether
the current PSW specifies the EC or BC mode.
The channel-mask bits in control register 2 start
at bit position 0 and extend for as many contiguous
bit positions as the number of channels provided.
The assignment is such that a bit is assigned to the
channel whose address is equal to the position of
the bit in control register 2. Channel-mask bits for
installed channels are initialized to one. The state
of the channel-mask bits for unavailable channels is
unpredictable.
When the current PSW specifies the EC mode,
each channel is controlled by the I/O-mask bit,
PSW bit 6, and by the corresponding channel-mask
bit in control register 2; the channel can cause an
interruption only when the I/O-mask bit is one and
the corresponding channel-mask bit is one.
When the current PSW specifies the BC mode,
interruptions from channels 6 and up are controlled
by the I/O-mask bit, PSW bit 6, in conjunction
with the corresponding channel-mask bit: the
channel can cause an interruption only when the
II
O-mask bit is one and the corresponding
channel-mask bit is one. Interruptions from
channels 0-5 are controlled by channel-mask bits
0-5 in the PSW: an interruption can occur only
when the mask bit corresponding to the channel is
one. In the BC mode, bits 0-5 in control register 2
do not participate in controlling I/O interruptions;
they are, however, preserved in the control register
if the corresponding channels are installed.
Machine-Check Interruption
The machine-check interruption is a means for
reporting to the program the occurrence of
equipment malfunctions. Information is provided
to assist the program in determining the location of
the fault and extent of the damage.
A machine-check interruption causes the old
PSW to be stored at location 48 and a new PSW to
be fetched from location 112. When the old PSW
specifies the BC mode, the contents of the
interruption-code and ILC fields in the old PSW
are unpredictable.
The cause and severity of the malfunction are
identified by a 64-bit machine-check-interruption
code stored at locations 232-239. Further
information identifying the cause of the
interruption and the location of the fault may be
stored at locations 216-511.
The interruption action and the storing of the
associated information are under the control of
Chapter 6. Interruptions
6-9
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