Download Print this page

IBM 4300 Manual page 74

Processors principles of operation for ecps: vse mode
Hide thumbs Also See for 4300:

Advertisement

Chapter 6. Interruptions
Contents
6-1
6-5
6-4
6-4
6-5
6-5
6-6
6-7
6-8
6-8
6-8
6-8
6-8
6-9
6-9
6-10
6-6
6-7
6-10
6-10
6-11
6-11
6-11
The interruption facility permits the CPU to change
its state as a result of conditions external to the
system, within the system, or within the CPU itself.
To permit fast response to conditions of high
priority and immediate recognition of the type of
condition, interruption conditions are grouped into
six classes: external, input/output, machine check,
program, restart, and supervisor call.
Interruption Action
An interruption consists in storing the current PSW
as an old PSW, storing information identifying the
cause of the interruption, and fetching a new PSW.
Processing resumes as specified by the new PSW.
The old PSW stored on an interruption normally
contains the address of the instruction that would
have been executed next had the interruption not
occurred, thus permitting resumption of the
interrupted program. For program and
6-11
6-12
6-12
6-13
6-13
6-11
6-12
6-12
6-12
6-12
6-13
6-13
6-14
6-14
6-14
6-14
6-14
6-15
6-18
6-18
6-19
6-16
supervisor-call interruptions, the information stored
also contains a code that identifies the length of
the last-executed instruction, thus permitting the
program to respond to the cause of the
interruption. In the case of some program
conditions for which the normal response is
reexecution of the instruction causing the
interruption, the instruction address directly
identifies the instruction last executed.
Except for restart, an interruption can take place
only when the CPU is in the operating state. The
restart interruption can occur with the CPU in
either the stopped or operating state.
The details of source identification, location
determination, and instruction execution are
explained in later sections and are summarized in
the figure "Interruption Action. "
6-1

Advertisement

loading