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storage (continued)
error
11-10
sequence of references to
5-9
location not provided
3-3
logical validity bit for
11-11
main
3-1
manual control of size
13-4
operand
5-3
consistency
5-11
fetch reference
5-10
store reference
5-10
update reference
5-11
protection
3-7
real
3-4
sequence of references
5-8
shared, examples
A-32
size of
3-3
validation
11-3
virtual
3-4
volatile
3-3
STORE (ST) binary instruction
7-31
STORE (STD,STE) floating-point instructions
STORE CAPACITY COUNTS (STCAP)
instruction
10-11
9-13
STORE CHANNEL ID (STIDC) instruction
12-23
STORE CHARACTER (STC) instruction
7-32
STORE CHARACTERS UNDER MASK (STCM)
instruction
7-32
examples
A-21
STORE CLOCK (STCK) instruction
7-32
STORE CLOCK COMPARATOR (STCKC)
instruction
10-11
STORE CONTROL (STCTL) instruction
STORE CPU ID (STIDP) instruction
STORE CPU TIMER (STPT) instruction
STORE HALFWORD (STH) instruction
STORE MULTIPLE (STM) instruction
example
A-22
store reference
5-10
access exceptions for
6-15
10-12
10-12
10-13
7-33
7-33
STORE THEN AND SYSTEM MASK (STNSM)
instruction
10-13
STORE THEN OR SYSTEM MASK (STOSM)
instruction
10-13
string of interruptions
by clock comparator
by CPU timer
4-20
subchannel
12-4
4-2, 6-19
4-18
not operational (I/O-system state)
working (I/O-system state)
12-10
subchannel key
in CAW
12-28
in CSW
12-47
contents of
12-56
validity flag for
12-61
used as access key
3-7
12-10
used for initial program loading
4-24
subclass-mask bits
6-7
external-interruption
6-7
machine-check
11-12
subroutine linkage
5-5
SUBTRACT (S,SR) binary instructions
7-33
SUBTRACT DECIMAL (SP) instruction
8-11
SUBTRACT HALFWORD (SH) instruction
7-34
SUBTRACT LOGICAL (SL,SLR) instructions
7-34
SUBTRACT NORMALIZED (SD,SDR,SE,SER,SXR)
instructions
9-14
SUBTRACT UNNORMALIZED (SU,SUR,SW,SWR)
instructions
9-14
successful branching (PER event)
4-11
SUPERVISOR CALL (SVC) instruction
7-34
supervisor-call interruption
6-18
supervisor state
4-5, 4-6
suppress-length-indication (SLI) flag in CCW
12-29
suppression of instruction
5-5
exceptions to
5-7
swapping
by COMPARE (DOUBLE) AND SWAP
instructions
7 -11
by EXCLUSIVE OR instruction
7-17
synchronization, CPU timer with time-of-day
clock
4-19
system
damage
11-8
manual control of
mask (in PSW)
validity bit for
13-1
4-3
11-10
organization
2-1
recovery
11-9
reset
(see
resets)
I/O
(see
I/O-system reset)
system-reset-clear key
13-5
system-reset-normal key
13-5
System/370 mode
1-1
selection of
13-2
t
target instruction
(see
EXECUTE instruction)
termination
code (in limited channel logout)
of instruction
5-6
TEST AND SET (TS) instruction
TEST CHANNEL (TCH) instruction
TEST I/O (TIO) instruction
12-25
12-61
7-35
12-24
function performed by CLEAR
I/O'
instruction
12-14
test indicator
13-5
TEST UNDER MASK (TM) instruction
example
A-24
TIC (transfer-in-channel) I/O command
time-of-day (TOD) clock
4-16
effect of power-on reset
4-24
manual control for
13-5
setting and storing
4-17
state
4-16
effect on interval timer
4-20
unique values
4-17
validation
11-4
timeout, channel
12-4
timer
CPU
(see
CPU timer)
interval
(see
interval timer)
timing f acili ties
4-16
damage
11-9
for time-of-day dock
4-16
TOD clock
(see
time-of-day clock)
TOD-clock control
13-5
enables time-of-day clock
4-17
7-35
12-39
transfer-in-channel (TIC) I/O command
12-39
TRANSLATE (TR) instruction
7-36
example
A-22
TRANSLATE AND TEST (TRT) instruction
7-36
example
A-23
trial execution
5-7
true zero
9-1
two's complement binary notation
7-2
examples
A-2
Index
X-II
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