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Machine-Check Mask (M): Bit 13 controls
whether the CPU is enabled for interruption by
machine-check conditions. When the bit is zero, a
machine-check interruption cannot occur. When
the bit is one, machine-check interruptions due to
system damage and instruction-processing damage
are permitted, but interruptions due to other
machine-cheek-subclass conditions are subject to
the subclass-mask bits in control register 14.
Wait State (W): When bit 14 is one, the CPU is
waiting; that is, no instructions are processed by
the CPU, but interruptions may take place. When
bit 14 is zero, instruction fetching and execution
occur in the normal manner. The wait indicator is
on when the bit is one.
Problem State (P): When bit 15 is one, the CPU
is in the problem state. When bit 15 is zero, the
CPU is in the supervisor state. In the supervisor
state, all instructions are valid. In the problem
state, only those instructions are valid that cannot
be used to affect the system integrity. The
instructions that are not valid in the problem state
are called privileged instructions. When a CPU in
the problem state attempts to execute a privileged
instruction, a privileged-operation exception is
recognized, and a program interruption takes place.
Condition Code (CC): Bits 18 and 19 are the two
bits of the condition code. The condition code is
set to a value of 0, 1,2, or 3, depending on the
result obtained in executing certain instructions.
Most arithmetic and logical operations, as well as
some other operations, set the condition code. The
instruction BRANCH ON CONDITION can
specify any selection of the condition-code values
as a criterion for branching. A table in Appendix
C summarizes the condition-code values that may
be set for all instructions which set the condition
code of the PSW.
Program Mask: Bits 20-23 are the four
program-mask bits. Each bit is associated with a
program exception, as follows:
Program-
Mask Bit
Program Exception
20
Fixed-point overflow
21
Decimal overflow
22
Exponent underflow
23
Significance
When the mask bit is one, the exception results
in an interruption. When the mask bit is zero, no
interruption occurs. The setting of the exponent-
underflow-mask bit or the significance-mask bit
also determines the manner in which the operation
is completed when the corresponding exception
occurs.
Instruction Address: Bits 40-63 form the
instruction address. This address designates the
location of the leftmost byte of the next
instruction.
Bit positions 0, 2-5, 16, 17, and 24-39 are
unassigned and must contain zeros. A specification
exception is recognized when these bit positions do
not contain zeros.
Chapter 4. Control
4-5
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