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2. Since the mask bits in control registers are not
changed as part of the interruption procedure,
these masks cannot be used to prevent an
interruption immediately after a previous
interruption in the same class. The mask bits in
control registers provide a means for selectively
enabling the CPU for some sources and
disabling it for others within the same class.
Instruction-Length Code
The instruction-length code (ILC) occupies two bit
positions and provides the length of the last
instruction executed.
It
permits identifying the
instruction causing the interruption when the
instruction address in the old PSW designates the
next sequential instruction. The ILC is provided
also by the BRANCH AND LINK instructions.
When the old PSW specifies the EC mode, the
ILC for program and supervisor-call interruptions is
stored in bit positions 5 and 6 of the bytes at
locations 137 and 141, respectively. For external,
110, machine-check, and restart interruptions, the
ILC is not stored since it cannot be related to the
length of the last-executed instruction.
When the old PSW specifies the BC mode, the
lLC is stored in bit positions 32 and 33 of that
PSW. The ILC is meaningful, however, only after
a supervisor-call or program interruption. For
machine-check, external,
1/0,
and restart
interruptions, the ILC does not indicate the length
of the last-executed instruction and is
unpredictable. Similarly, the ILC is unpredictable
in the PSW stored during execution of the
machine-save function and when the PSW is
displayed.
For supervisor-call and program interruptions, a
nonzero ILC identifies in halfwords the length of
the instruction that was last executed. Whenever
an instruction is executed by means of EXECUTE,
instruction-length code 2 is set to indicate the
length of EXECUTE and not that of the target
instruction.
The value of a nonzero instruction-length code is
related to the leftmost two bits of the instruction.
The value is not contingent on whether the
operation code is assigned or on whether the
instruction is installed. The following table
summarizes the meaning of the instruction-length
code:
ILC
Instr
Bits
Instruction
Decimal Binary
0-1
Length
0
00
Not available
1
01
00
One halfword
2
10
01
Two halfwords
2
10
10
Two ha lfwor ds
3
11
11
Three ha lfwords
Zero ILC
Instruction-length code 0, after a program
interruption, indicates that the location of the
instruction causing the interruption is not made
available. to the program.
An ILC of
°
occurs when a specification
exception is recognized that is due to a
PSW-format error, other than one due to an odd
instruction address, and the invalid PSW has been
introduced by LOAD PSW or an interruption. (See
the section "Exceptions Associated with the PSW"
later in this chapter.) In the case of LOAD PSW
the address of the instruction has been replaced by
the instruction address of the new PSW. When the
invalid PSW is introduced by an interruption, the
PSW -format error cannot be attributed to an
instruction.
In the case of LOAD PSW and the
supervisor-call interruption, a PER event may be
indicated concurrently with a specification
exception having an ILC of 0.
ILC on Instruction-Fetching Exceptions
When a program interruption occurs because of an
exception that prohibits access to the instruction,
the instruction-length code cannot be set on the
basis of the first two bits of the instruction. As far
as the significance of the ILC for this case is
concerned, the following two situations are
distinguished:
1 . When an odd instruction address causes a
specification exception to be recognized or
when an addressing or protection exception is
encountered on fetching an instruction, the ILC
is set to 1, 2, or 3, indicating the multiple of 2
by which the instruction address has been
incremented.
It
is unpredictable whether the
instruction address is incremented by 2, 4, or 6.
By reducing the instruction address in the old
Chapter 6. Interruptions
6-5
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