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RZ+1
Pad
Second-Operand Length
o
8
31
The movement starts at the left end of both
fields and proceeds to the right. The operation is
ended when the number of bytes specified by bit
positions 8-31 of register Rl
+
1 have been moved
into the first-operand location. If the second
operand is shorter than the first operand, the
remaining rightmost bytes of the first-operand
location are filled with the padding byte.
As part of the execution of the instruction, the
values of the two length fields are compared for the
setting of the condition code, and a check is made
for destructive overlap of the operands. Operands
are said to overlap destructively when the
first-operand location is used as a source after data
has been moved into it. When the operands
overlap destructively, no movement takes place,
and condition code 3 is set.
Operands do not overlap destructively, and
movement is performed, if the leftmost byte of the
first operand does not coincide with any of the
second-operand bytes participating in the operation
other than the leftmost byte of the second operand.
When an operand wraps around from location
16,777,215 to location 0, operand bytes in
locations up to and including 16,777,215 are
considered to be to the left of bytes in locations
from 0 up.
When the length specified by bit positions 8-31
of register R
1
+
1 is zero, no movement takes place,
and condition code 0 or 1 is set to indicate the
relative values of the lengths.
The execution of the instruction is interruptible.
When an interruption occurs other than one that
causes termination, the contents of registers Rl
+
1
and R2
+
1 are decremented by the number of bytes
moved, and the contents of register Rl and R2 are
incremented by the same number, so that the
instruction, when reexecuted, resumes at the point
of interruption. The high-order bits which are not
part of the address in registers Rl and R2 are set to
zeros; the contents of the high-order byte of
registers Rl
+
1 and R 2
+
1 remain unchanged; and
the condition code is unpredictable.
If
the
operation is interrupted during padding, the length
field in register R2
+
1 is 0, the address in register
R2 is incremented by the original contents of
register R2
+
1 , and registers R
1
and R
1
+
1 reflect
the extent of the padding operation.
When the first-operand location includes the
location of the instruction, the instruction may be
refetched from storage and reinterpreted even in
the absence of an interruption during execution.
The exact point in the execution at which such a
refetch occurs is unpredictable.
As viewed by channels and other CPUs, that
portion of the first operand which is filled with the
padding byte is not necessarily stored into in a
left-to-right direction and may appear to be stored
more than once.
At the completion of the operation, the length in
register Rl
+
1 is decremented by the number of
bytes stored at the first-operand location, and the
address in register R
1
is incremented by the same
amount. The length in register R2
+
1 is
decremented by the number of bytes moved out of
the second-operand location, and the address in
register R2 is incremented by the same amount.
The bits which are not part of the address in
registers R
1
and R2 are set to zeros, including the
case when one or both of the original length values
are zeros or when condition code 3 is set. The
contents of bit positions 0-7 of registers R
1
+
1 and
R
2
+
1 remain unchanged.
When condition code 3 is set, no exceptions
associated with operand access are recognized.
When the length of an operand is zero, no access
exceptions for that operand are recognized.
Similarly, when the second operand is longer than
the first operand, access exceptions are not
recognized for the part of the second-operand field
that is in excess of the first-operand field. For
operands longer than 2,048 bytes, access exceptions
are not recognized for locations more than 2,048
bytes beyond the current location being processed.
Access exceptions are not recognized for an
operand if the R field associated with that operand
is odd. Also, when the R
1
field is odd, PER
storage alteration is not recognized, and no change
bits are set.
Resulting Condition Code:
o
First-operand and second-operand lengths are
equal
1
First-operand length is low
2
First-operand length is high
3
No movement performed because of
destructive overlap
Program Exceptions:
Access (fetch, operand 2; store, operand 1)
Specification
Chapter 7. General Instructions
7-23
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