Advertisement
all these cases, the program old PSW
associated with the program interruption for
the PER event may indicate that the CPU
was disabled for that type of PER event.
b.
An instruction-fetching event may be
recognized during execution of a LOAD
CONTROL instruction which also changed
the value of the PER-event masks in
control register 9 or the addresses in
control registers 10 and 11 controlling
indication of instruction-fetching events.
2. No instructions can both change the values of
general-register-alteration masks and cause a
general-register-alteration event to be
recognized.
3. When a PER interruption occurs during the
execution of an interruptible instruction, the
ILC indicates the length of that instruction or
EXECUTE, as appropriate. When a PER
interruption occurs as a result of LOAD PSW
or SUPERVISOR CALL, the ILC indicates the
length of these instructions or EXECUTE, as
appropriate, unless a concurrent specification
exception on LOAD PSW calls for an ILC of O.
4. When a PER interruption is caused by
branching, the PER address identifies the
branch instruction (or EXECUTE, as
appropriate), whereas the old PSW points to
the next instruction to be executed. When the
interruption occurs during the execution of an
interruptible instruction, the PER address and
the instruction address in the old PSW are the
same.
Storage-Area Designation
Two of the PER events-instruction fetching and
storage alteration-involve the designation of an
area in storage. The storage area monitored for the
references starts at the location designated by the
starting address in control register 10 and extends
up to and including the location designated by the
ending address in control register 11. The area
extends to the right of the starting address.
The set of addresses monitored for
instruction-fetching and storage-alteration events
wraps around at address 16,777,215; that is,
address 0 is considered to follow address
16,777,215. When the starting address is less than
the ending address, the area is contiguous. When
the starting address is greater than the ending
address, the set of locations monitored includes the
area from the starting address to address
16,777,215 and the area from address 0 to, and
including, the ending address. When the starting
address is equal to the ending address, only the
location designated by that address is monitored.
The monitoring of storage alteration and
instruction fetching is performed by comparing all
24 bits of the monitored address with the starting
and ending addresses.
PER Events
Successful Branching
Execution of a successful branch operation causes a
program-event interruption if bit 0 of the
PER-eve nt-mask field is one and the PER mask in
the PSW is one.
A successful branch occurs whenever one of the
following instructions causes control to be passed to
the instruction designated by the branch address:
BRANCH ON CONDITION
BRANCH AND LINK
BRANCH ON COUNT
BRANCH ON INDEX HIGH
BRANCH ON INDEX LOW OR EQUAL
The branch event is also indicated by an
emulation instruction when the emulation
instruction itself causes a branch. That is, the
branch event is indicated when the location of the
next instruction executed by the CPU after leaving
emulation mode does not immediately follow the
location of the emulation instruction.
The event is indicated by setting bit 0 of the
PER code to one.
Instruction Fetching
Fetching the first byte of an instruction from the
storage area designated by the contents of control
registers 10 and 11 causes a program-event
interruption if bit 1 of the PER-event-mask field is
one and the PER mask in the PSW is one.
A PER event for instruction fetching is
recognized whenever the CPU executes an
instruction whose initial byte is located within the
monitored area. When the instruction is executed
by means of EXECUTE, a PER event is recognized
when the first byte of the EXECUTE instruction or
the target instruction or both is located in the
monitored area.
The event is indicated by setting bit 1 of the
PER code to one.
Storage Alteration
Storing of data by the CPU in the storage area
designated by the contents of control registers 10
and 11 causes a program-event interruption if bit 2
Chapter 4. Control
4-11
Advertisement
Chapters
