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Stopped State
The state of the CPU is changed from operating to
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stopped by the stop function. The stop function is
performed when:
• The stop key is activated while the CPU is in the
operating state.
• The CPU has finished the execution of a unit of
operation initiated by performing the start
function with the rate control set to instruction
step.
When the stop function is performed, the
transition from the operating to the stopped state
occurs at the end of the current unit of operation.
When the wait-state bit of the PSW is one, the
transition takes place immediately, provided no
interruptions are pending for which the CPU is
enabled. In the case of interruptible jnstructions,
the amount of data processed in a unit of operation
depends on the particular instruction and may
depend on the model.
Before entering the stopped state, all pending
allowed interruptions are taken while the CPU is
still in the operating state. They cause the old
PSW to be stored and the new PSW to be fetched
before the stopped state is entered. When the CPU
is in the stopped state, interruption conditions
remain pending.
The CPU is also placed in the stopped state:
• When a reset is completed, except when the reset
operation is performed as part of initial program
loading, and
• When an address comparison indicates equality
and stopping on the match is specified
The execution of resets is described in the
section "Resets" in this chapter, and address
comparison is described in the section
"Address-Compare Controls" in Chapter 13,
"Operator Facilities."
Operating State
The state of the CPU is changed from stopped to
operating when the start function is performed or
when a restart interruption occurs. However, the
effect of performing the start function is
unpredictable when the stopped state was entered
by means of a reset.
The start function is performed on the CPU in
the stopped state when the start key is activated.
When the wait-state bit is one and the rate
control is set to instruction step, the start function
causes no instruction to be executed, but all
pending allowed interruptions are taken before the
CPU returns to the stopped state.
4-2
IBM 4300 Processors Principles of Operation
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Load State
The CPU enters the load state when the
load-normal or load-clear key is activated (see the
section "Initial Program Loading" in this chapter).
When the initial-program-Ioading operation is
completed successfully, the CPU state changes from
load to operating, provided the rate control is set to
process; if the rate control is set to instruction step,
the CPU state changes from load to stopped.
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Check-Stop State
The check-stop state, which the CPU enters on
certain types of machine malfunction, is described
in Chapter 11, "Machine-Check Handling."
Programming Notes
1. Except for the relationship between execution
time and real time, the execution of a program
is not affected by stopping the CPU.
2. When, because of a machine malfu.nction, the
CPU is unable to end the execution of an
instruction, the stop function is ineffective, and
a reset function has to be invoked instead. A
similar situation occurs when an unending
string of interruptions results from a PSW with
a PSW -format error of the type that is
recognized early, or from a persistent
interruption condition, such as one due to the
CPU timer.
3. Input/output operations continue to completion
after the CPU enters the stopped state. The
interruption conditions due to completion of
I/O operations remain pending when the CPU
is in the stopped state.
Program-Status Word
The current program-status word (PSW) contains
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information required for the execution of the
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currently active program. The PSW is 64 bits in
length and includes the instruction address,
condition code, and other control fields. In
general, the PSW is used to control instruction
sequencing and to hold and indicate much of the
status of the CPU in relation to the program
currently being executed. Additional control and
status information is contained in control registers
and permanently assigned storage locations.
Control is switched during an interruption of the
CPU by storing the current PSW, so as to preserve
the status of the CPU, and then loading a new
PSW.
The status of the CPU can be changed by
loading a new PSW or part of a PSW.
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