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expected to interfere with the current
machine-check processing. If, however, the
CPU also makes a reference to the area of
storage containing the error before re-enabling
machine-check interruptions, another
instruction-processing-damage condition is
created, which is treated as an exigent
condition and causes the CPU to enter the
check-stop state.
Interruption Action
A machine-check interruption causes the following
actions to be taken. The PSW reflecting the point
of interruption is stored as the machine-check old
PSW at location 48. The contents of other
registers are stored in register-save areas at
locations 216-231 and 352-511. After the
contents of the registers are stored in register-save
areas, the registers are validated with the contents
being unpredictable. A failing-storage address, if
any, is stored at location 248. Then a
machine-check-interruption code (MCIC) of eight
bytes is placed at location 232. The new PSW is
fetched from location 112.
The fields accessed during the machine-check
interruption are summarized in the figure
"Machine-Check-Interruption Locations."
If
the machine-check-interruption code cannot
be stored successfully or the new PSW cannot be
fetched successfully, the CPU enters the check-stop
state.
A repressible machine-check condition can
initiate a machine-check interruption only if both
PSW bit 13 is one and the associated subclass mask
bit in control register 14 is also one. When it
occurs, the interruption does not terminate the
execution of the current instruction; the
interruption is taken at a normal point of
interruption, and no program or supervisor-call
interruptions are eliminated.
If
the machine check
occurs during the execution of a machine function,
such as a CPU-timer update, the machine-check
interruption takes place after the machine function
has been completed.
When the CPU is disabled for a particular
repressible machine-check condition, the condition
remains pending. Only one repressible condition is
held pending for each subclass, regardless of the
number of conditions that may have been detected
for that subclass.
When a repressible machine-check interruption
occurs because the interruption condition is in a
subclass for which the CPU is enabled, pending
conditions in other subclasses may also be indicated
in the same interruption code, even though the
CPU is disabled for those subclasses. All indicated
conditions are then cleared.
I
If
a machine check which is to be reported as a
system-recovery condition is detected during the
execution of the interruption procedure due to a
previous machine-check condition, the
system-recovery condition may be combined with
the other conditions, discarded, or held pending.
An exigent machine-check condition can cause a
machine-check interruption only when PSW bit 13
is one. When it occurs, the interruption terminates
the execution of the current instruction and may
eliminate the program and supervisor-call
interruptions, if any, that would have occurred if
execution had continued. Proper execution of the
interruption steps, including the storing of the old
PSW and other information, depends on the nature
of the malfunction. When an exigent
machine-check condition occurs during the
execution of a machine function, such as a
(Fetched)
Starting
Length
Information Stored
Location
in Bytes
Old PSW
48
8
New PSW (fetched)
112
8
Machine-cheek-interruption code
232
8
Failing-storage address
248
4
Register-save areas
CPU timer
216
8
Clock comparator
224
8
Floating-point registers 0, 2, 4, 6
352
32
General registers 0-15
384
64
Control registers 0-15
448
64
Machine-Cheek-Interruption Locations
11-6
IBM 4300 Processors Principles of Operation
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