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IBM 4300 Manual page 291

Processors principles of operation for ecps: vse mode
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Mne-
Op
Page
Name
monic
Characteristics
Code
No.
SET CLOCK COMPARATOR
SCKC
S
P A SP
B206
10-9
SET CPU TIMER
SPT
S
P A SP
B208
10-9
SET PAGE BITS
SPB
RS
C
P Al
B5
10-9
SET PROGRAM MASK
SPM
RR
L
04
7-28
SET PSW KEY FROM ADDRESS
SPKA S
P
B20A
10-10
SET STORAGE KEY
SSK
RR
P Al SP
08
10-10
SET SYSTEM MASK
SSM
S
P A SP
SO
80
10-11
SHIFT AND ROUND DECIMAL
SRP
SS
C
A
D OF
ST FO
8-10
SHIFT LEFT DOUBLE
SLDA RS
C
SP
IF
R
8F
7-28
SHIFT LEFT DOUBLE LOGICAL
SLDL
RS
SP
R
80
7-29
SHIFT LEFT SINGLE
SLA
RS
C
IF
R
8B
7-29
SHIFT LEFT SINGLE LOGICAL
SLL
RS
R
89
7-30
SHIFT RIGHT DOUBLE
SRDA RS
C
SP
R
8E
7-30
SHIFT RIGHT DOUBLE LOGICAL
SRDL
RS
SP
R
8C
7-30
SHIFT RIGHT SINGLE
SRA
RS
C
R
8A
7-31
SHIFT RIGHT SINGLE LOGICAL
SRL
RS
R
88
7-31
START I/O
SIO
S
C
P
$
9COO*
12-21
START I/O FAST RELEASE
SIOF
S
C
P
$
9C01*
12-21
STORE
ST
RX
A
ST 50
7-31
STORE ( long)
STD
RX
A SP
ST 60
9-13
STORE (shor t)
STE
RX
A SP
ST 70
9-13
STORE CAPACITY COUNTS
STCAP S
P A
ST B21F
10-11
STORE CHANNEL 10
STIDC S
C
P
$
B203
12-23
STORE CHARACTER
STC
RX
A
ST 42
7-32
STORE CHARACTERS UNDER MASK
STCM RS
A
ST BE
7-32
STORE CLOCK
STCK S
C
A
$
ST B205
7-32
STORE CLOCK COMPARATOR
STCKC S
P A SP
ST B207
10-11
STORE CONTROL
STCTL RS
P A SP
ST B6
10-12
STORE CPU 10
STIDP S
P A SP
ST B202
10-12
STORE CPU TIMER
STPT S
P A SP
ST B209
10-13
STORE HALFWORD
STH
RX
A
ST 40
7-33
STORE MULTIPLE
STM
RS
A
ST 90
7-33
STORE THEN AND SYSTEM MASK
STNSM SI
P A
ST AC
10-13
STORE THEN OR SYSTEM MASK
STOSM SI
P A SP
ST AD
10-13
SUBTRACT
SR
RR
C
IF
R
1B
7-33
SUBTRACT
S
RX
C
A
IF
R
5B
7-33
SUBTRACT DECIMAL
SP
SS
C
A
0
OF
ST FB
8-11
SUBTRACT HALFWORD
SH
RX
C
A
IF
R
4B
7-34
SUBTRACT LOGICAL
SLR
RR
C
R
1F
7-34
SUBTRACT LOGICAL
SL
RX
C
A
R
5F
7-34
SUBTRACT NORMALIZED (extended)
SXR
RR
C
SP EU EO
LS
37
9-14
SUBTRACT NORMALIZED (long)
SDR
RR
C
SP EU EO
LS
2B
9-14
SUBTRACT NORMALIZED (long)
SO
RX
C
A SP EU EO
LS
6B
9-14
SUBTRACT NORMALIZED (short)
SER
RR
C
SP EU EO
LS
3B
9-14
SUBTRACt NORMALIZED ( short)
SE
RX
C
A SP EU EO
LS
7B
9-14
SUBTRACT UNNORMALIZED ( long)
SWR
RR
C
SP
EO
LS
2F
9-14
SUBTRACT UNNORMALIZED ( long)
SW
RX
C
A SP
EO
LS
6F
9-14
SUBTRACT UNNORMALIZED (short)
SUR
RR
C
SP
EO
LS
3F
9-14
SUBTRACT UNNORMALIZED (short)
SU
RX
C
A SP
EO
LS
7F
9-14
SUPERVISOR CALL
SVC
RR
$
OA
7-34
TEST AND SET
TS
S
C
A
$
ST 93
7-35
TEST CHANNEL
TCH
S
C
P
$
9FOO;t
12-24
TEST I/O
TIO
S
C
P
$
9000*
12-25
TEST UNDER MASK
TM
S I C
A
91
7-35
TRANSLATE
TR
SS
A
ST DC
7-36
TRANSLATE AND TEST
TRT
SS
C
A
R
DO
7-36
UNPACK
UNPK SS
A
ST F3
7-37
ZERO AND ADD
ZAP
S5
C
A
0
OF
5T F8
8-11
Instructions Arranged
by
Name (Part 3 of 3)
B-4
IBM 4300 Processors Principles of Operation

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