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User's Manual
A2 Processor
Table 7-3. Interrupt and Exception Types
Offset
Interrupt Type
Notes:
1. Although it is not specified as part of the Power ISA, it is common for system implementations to provide, as part of the interrupt
controller, independent mask and status bits for the various sources of critical input and external input interrupts.
2. Machine check interrupts are not classified as asynchronous nor synchronous. They are also not classified as critical or noncriti-
cal, because they use their own unique set of Save/Restore Registers, MCSRR0/1. See Machine Check Interrupts on page 296,
and Machine Check Interrupt on page 327.
3. Debug exceptions have special rules regarding their interrupt classification (synchronous or asynchronous and precise or impre-
cise), depending on the particular debug mode being used and other conditions (see Debug Interrupt on page 347).
4. In general, when an interrupt causes a particular ESR(GESR) bit or bits to be set as indicated in the table, it also causes all other
ESR(GESR) bits to be cleared. If no ESR(GESR) setting is indicated for any of the exception types within a given interrupt type,
the ESR(GESR) is unchanged for that interrupt type.
The syntax for the ESR(GESR) setting indication is as follows:
[xxx] means ESR(GESR)[xxx] can be set.
[xxx,yyy,zzz] means any one (or none) of ESR(GESR)[xxx] or ESR(GESR)[yyy] or ESR(GESR)[zzz] can be set, but never more
than one.
{xxx,yyy,zzz} means that any combination of ESR(GESR)[xxx], ESR(GESR)[yyy], and ESR(GESR)[zzz] can be set, including all
or none.
xxx means ESR[xxx] will be set.
5. The byte ordering exception type of data storage interrupts can only occur when the A2 core is connected to a floating-point unit or
auxiliary processor, and then only when executing FP or AXU load or store instructions. See Data Storage Interrupt on page 330
for more detailed information about these kinds of exceptions.
6. The byte ordering exception type of instruction storage interrupts are defined by the Power ISA, but cannot occur within the A2
core. The core is capable of executing instructions from both big-endian and little-endian code pages.
7. An attempt to execute an instruction that is not provided by the implementation results in an illegal instruction program type of
interrupt.
8. Floating-point unavailable and auxiliary processor unavailable interrupts, as well as floating-point enabled and auxiliary processor
enabled exception type of program interrupts, can only occur when the A2 core is connected to a floating-point unit or an auxiliary
processor, and then only when executing instruction opcodes that are recognized by the floating-point unit or auxiliary processor,
respectively.
7.6.1 Critical Input Interrupt
A critical input interrupt occurs when no higher priority exception exists, a critical input exception is presented
to the interrupt mechanism, and (MSR[CE] or MSR[GS]) = 1. A critical input exception is caused by the acti-
vation of an asynchronous input to the A2 core. Although the only mask for this interrupt type within the core
is the MSR[CE] bit, system implementations typically provide an alternative means for independently masking
the interrupt requests from the various devices that collectively can activate the A2 core's critical input inter-
rupt request input.
Note: MSR[CE] also enables other interrupts. See Table 7-3 Interrupt and Exception Types on page 323.
Note: When a critical input interrupt occurs, the interrupt processing registers are updated as indicated
below (all registers not listed are unchanged), and instruction execution resumes at address
IVPR[IVP] || 0x020.
CPU Interrupts and Exceptions
Page 326 of 864
(Sheet 4 of 4)
Exception Type
ESR (GESR)
(See Note 4)
October 23, 2012
Version 1.3
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