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Situations
Contents of Field
Channel-control check
Status stored by START I/O or
START I/O FAST RELEASE
Status stored by HALT I/O or
HALT DEVICE
Program check
Protection check
Chaining check
Termination under count control
Termination by I/O device
Termination by HALT I/O or
HALT DEVICE
Unpredictable
Unchanged
Unchanged
Unpredictable
Unpredictable
Unpredictable
Correct
Correct
Unpredictable
Unpredictable
Termination by CLEAR I/O
Suppression of command
chaining due to unit check
or unit exception with device
end or control-unit end
Correct. Residual count of last
CCW used in the completed
operation.
Termination on command chaining
by busy, unit check, or unit
exception
Correct. Original count of
CCW specifying the new
operation.
Deferred condition code 1 or 3
Correct. Original count of CCW
for START I/O FAST RELEASE
PCI flag in CCW
Interface-control check
Channel end after HALT I/O
specifying the new operation.
on selector channel
Channel end after CLEAR I/O
Control-unit end
Device end
Attention
Busy
Status modifier
Contents of the Count Field in the CSW
Unpredictable
Unpredictable
Zero
Zero
Zero
Zero
Zero
Zero
Zero
conclusion and mayor may not indicate incorrect
length. When a data error has been detected and
the operation is concluded prematurely because of a
program check, protection check, or chaining check,
both data check and the programming error are
identified.
If
the CCW fetched on command chaining has
the PCI flag set to one but a programming error in
the contents of the CCW precludes the initiation of
the operation, it is unpredictable whether the PCI
bit is one in the CSW associated with the
interruption condition. Similarly, if a programming
error in the contents of the CCW causes the
command to be rejected during execution of
START I/O or START I/O FAST RELEASE, the
CSW stored by the instruction mayor may not
have the PCI bit set to one. Furthermore, when
the channel detects a programming error in the
CAW or in the first CCW, the PCI bit is
12-58
IBM 4300 Processors Principles of Operation
unpredictable in a CSW stored by START I/O or
STAR T I/O FAST RELEASE even when the PCI
flag is zero in the first C CW associated with the
instruction.
However, if the CCW fetched on command
chaining has the PCI flag set to one but an unusual
situation detected by the device precludes the
initiation of the operation, the PCI bit is one in the
CSW associated with the interruption condition.
Likewise, if device status causes the command to be
rejected during execution of START I/O or
START 1/ 0 FAST RELEASE, the CSW stored by
the instruction contains the PCI bit set to one.
Situations detected by the channel are not
related to those identified by the I/O device.
The figure
11
Contents of the CSW Status Fields
11
summarizes the handling of status bits. The figure
lists the states and activities that can cause status
indications to be created and the methods by which
these indications can be placed in the CSW.
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