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operation code. The operation code may not be
assigned, or the instruction with that operation
code may not be available on the CPU.
For the purpose of checking the operation code
of an instruction, the operation code is defined as
follows:
1. When the first eight bits of an instruction have
the value B2 (hex), the first 16 bits form the
operation code.
2. In all other cases, the first eight bits alone form
the operation code.
The operation is suppressed.
The instruction-length code is 1, 2, or 3.
Programming Notes
1. Some models may offer instructions not
described in this publication, such as those
provided for emulation or as part of special or
custom features. Consequently, operation
codes not described in this publication do not
necessarily cause an operation exception to be
recognized. Furthermore, these instructions
may cause modes of operation to be set up or
may otherwise alter the machine so as to affect
the execution of subsequent instructions. To
avoid causing such an operation, an instruction
with an operation code not described in this
publication should be issued only when the
specific function associated with the operation
code is desired.
2.
The operation code 00, with a two-byte
instruction format, currently is not assigned.
It
is improbable that this operation code will ever
be assigned.
3. In the case of I/O instructions with the values
9C, 9D, and 9E in bit positions 0-7, the value
of bit 15 is used to distinguish between two
instructions. Bits 8-14, however, are not
checked for zeros, and these operation codes
never cause an operation exception to be
recognized.
To ensure that presently written programs
run if and when the I/O operation codes (9C,
9D, 9E, and 9F) are extended further to
provide for new functions, only zeros should be
placed in the unused bit positions in the second
op-code byte. In accordance with these
recommendations, the operation codes for the
I/O instructions are shown as 9COO, 9COl,
9DOO, etc.
Page-Access Exception
A page-access exception is recognized when storage
is addressed either explicitly or implicitly by the
CPU and the addressed storage location is in a
page that is in the connected or disconnected state.
The exception is recognized as part of the
execution of the instruction when an attempt is
made to access either the instruction or operand
location. However, page-access exceptions are not
recognized for the page operands of the
instructions CLEAR PAGE, CONNECT PAGE,
DECONFIGURE PAGE, DISCONNECT PAGE,
MAKE ADDRESSABLE, and MAKE
UNADDRESSABLE.
The unit of operation is nullified, except for the
possible effects on storage described in the section
"Nontransparent Nullification" in this chapter.
The address of the storage location causing the
exception is stored at locations 145 -147, and zeros
are stored at location 144. The low-order 11 bits of
the address stored are unpredictable.
When the exception occurs during a reference to
an operand location, the instruction-length code
OLC) is 1, 2, or 3 and indicates the length of the
instruction causing the exception. When the
exception occurs during fetching of an instruction,
the ILC is 1,2, or 3, the value being unpredictable.
Page-State Exception
A page-state exception is recognized when the
target page of the CLEAR PAGE instruction is in
the disconnected state.
The operation is suppressed.
The instruction-length code is 2.
Page-Transition Exception
A page-transition exception can only be recognized
for instructions that cause a page-state transition.
These instructions are CONNECT PAGE,
DECONFIGURE PAGE, DISCONNECT PAGE,
MAKE ADDRESSABLE, and MAKE
UNADDRESSABLE.
The exception is recognized as part of the
execution of the instruction when attempting to
perform an invalid page-state transition. For the
definition of an invalid page-state transition, see
the section "Page States" in Chapter 3, "Storage."
The operation is suppressed.
The instruction-length code is 2.
PER Event
A PER event is recognized when program-event
recording is specified by the contents of control
registers 9-11 and one or more of these events
occur.
Chapter 6; Interruptions
6-13
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