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Mne-
Op
Name
monic
Characteristics
Code
MOVE (immediate)
MVI
SI
A
ST 92
MOVE INVERSE
MVCIN SS
A
ST E8
MOVE LONG
MVCL
RR
C
A SP
"
R ST OE
MOVE NUMERICS
MVN
SS
A
ST 01
MOVE WITH OFFSET
MVO
SS
A
ST F1
MOVE ZONES
MVZ
SS .
A
ST 03
MULTIPLY
MR
RR
SP
R
1C
MULTIPLY
M
RX
A SP
R
5C
MULTIPLY HALFWORD
MH
RX
A
R
4C
OR
OR
RR
C
R
16
OR
0
RX
C
A
R
56
OR (character)
DC
SS
C
A
ST 06
OR (immediate)
01
SI
C
A
ST 96
PACK
PACK
SS
A
ST F2
SET PROGRAM MASK
SPM
RR
L
04
SHIFT LEFT DOUBLE
SLDA RS
C
SP
IF
R
8F
SHIFT LEFT DOUBLE LOGICAL
SLDL
RS
SP
R
80
SHIFT LEFT SINGLE
SLA
RS
C
IF
R
8B
SHIFT LEFT SINGLE LOGICAL
SLL
RS
R
89
SHIFT RIGHT DOUBLE
SRDA RS
C
SP
R
8E
SHIFT RIGHT DOUBLE LOGICAL
SRDL
RS
SP
R
8C
SHIFT RIGHT SINGLE
SRA
RS
C
R
8A
SHIFT RIGHT SINGLE LOGICAL
SRL
RS
R
88
STORE
ST
RX
A
ST 50
STORE CHARACTER
STC
RX
A
ST 42
STORE CHARACTERS UNDER MASK
STCM
RS
A
ST BE
STORE CLOCK
STCK
S
C
A
$
ST B205
STORE HALFWORD
STH
RX
A
ST 40
STORE MULTIPLE
STM
RS
A
ST 90
SUBTRACT
SR
RR
C
IF
R
1B
SUBTRACT
S
RX
C
A
IF
R
5B
SUBTRACT HALFWORD
SH
RX
C
A
IF
R
4B
SUBTRACT LOGICAL
SLR
RR . C
R
1F
SUBTRACT LOGICAL
SL
RX
C
A
R
5F
SUPERVISOR CALL
SVC
RR
$
OA
TEST AND SET
TS
S
C
A
$
ST 93
TEST UNDER MASK
TM
SI
C
A
91
TRANSLATE
TR
SS
A
ST DC
TRANSLATE AND TEST
TRT
SS
C
A
R
DO
UNPACK
UNPK
SS
A
ST F3
Explanation:
A
Access exceptions
RR
RR instruction format
B
PER branch event
RS
RS instruction format
C
Condition code is set
RX
RX instruction format
0
Data exception
S
S instruction format
EX
Execute exception
SI
SI instruction format
IF
Fixed-point-overflow exception
SP
Specification exception
"
Interruptible instruction
SS
SS instruction format
IK
Fixed-point-divide exception
ST
PER storage-alteration event
L
New condition code loaded
~
1
Causes serial ization
MO
Monitor event
Causes serialization when the M1
R
PER general-register-alteration event
and R2 fields contain all ones
and all zeros, respectively
Summary of General Instructions (Part 2 of 2)
7-6
IBM 4300 Processors Principles of Operation
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