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IBM 4300 Manual page 293

Processors principles of operation for ecps: vse mode
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Mne-
Op
Page
monic
Name
Characteristics
Code
No.
IPK
INSERT PSW KEY
S
P
R
B20B
10-5
ISK
INSERT STORAGE KEY
RR
P Al SP
R
09
10-5
L
LOAD
RX
A
R
58
7-19
LA
LOAD ADDRESS
RX
R
41
7-19
LCDR
LOAD COMPLEMENT (long)
RR
C
SP
23
9-10
LCER
LOAD COMPLEMENT (short)
RR
C
SP
33
9-10
LCR
LOAD COMPLEMENT
RR
C
IF
R
13
7-19
LCn
LOAD CONTROL
RS
P A SP
B7
10-6
LD
LOAD (long)
RX
A SP
68
9-10
LDR
LOAD ( long)
RR
SP
28
9-10
LE
LOAD {short}
RX
A SP
78
9-10
LER
LOAD (short)
RR
SP
38
9-10
LFI
LOAD FRAME INDEX
RS
C
P
R
B8
10-6
LH
LOAD HALFWORD
RX
A
R
48
7-20
LM
LOAD MULTIPLE
RS
A
R
98
7-20
LNDR
LOAD NEGATIVE ( long)
RR
C
SP
21
9-11
LNER
LOAD NEGATIVE (short)
RR
C
SP
31
9-11
LNR
LOAD NEGATIVE
RR
C
R
11
7-20
LPDR
LOAD POSITIVE ( long)
RR
C
SP
20
9-11
LPER
LOAD POSITIVE (short)
RR
C
SP
30
9-11
LPR
LOAD POSITIVE
RR
C
IF
R
10
7-20
LPSW LOAD PSW
S
L
P A SP
$
82
10-7
LR
LOAD
RR
R
18
7-19
LRDR
LOAD ROUNDED (extended to long)
RR
SP
EO
25
9-11
LRER
LOAD ROUNDED (long to short)
RR
SP
EO
35
9-11
LTDR
LOAD AND TEST ( long)
RR
C
SP
22
9-10
LTER
LOAD AND TEST (short)
RR
C
SP
32
9-10
LTR
LOAD AND TEST
RR
C
R
12
7-19
M
MULTIPLY
RX
A SP
R
5C
7-26
MAD
MAKE ADDRESSABLE
S
C
P Al
PT
B21D
10-7
MC
MON /TOR CALL
SI
SP
MO
AF
7-21
MD
MULTIPLY (long)
RX
A SP EU EO
6C
9-12
MDR
MULTIPLY (long)
RR
SP EU EO
2C
9-12
ME
MULTIPLY (short to long)
RX
A SP EU EO
7C
9-12
MER
MULTIPLY (short to long)
RR
SP EU EO
3C
9-12
MH
MULTIPLY HALFWORD
RX
A
R
4C
7-26
MP
MULTIPLY DECIMAL
SS
A SP D
ST FC
8-9
MR
MULTIPLY
RR
SP
R
1 C
7-26
MUN
MAKE UNADDRESSABLE
S
C
P Al SP
PT
B21E
10-7
MVC
MOVE (character)
SS
A
ST D2
7-21
MVCIN MOVE INVERSE
SS
A
ST E8
7-22
MVCL
MOVE LONG
RR
C
A SP
II
R ST OE
7-22
MVI
MOVE (immediate)
SI
A
ST 92
7-22
MVN
MOVE NUMERICS
SS
A
ST Dl
7-24
MVO
MOVE WITH OFFSET
SS
A
ST Fl
7-25
MVZ
MOVE ZONES
SS
A
ST D3
7-26
MXD
MULTIPLY (long to extended)
RX
A SP EU EO
67
9-12
MXDR
MULTIPLY (long to extended)
RR
SP EU EO
27
9-12
MXR
MULTIPLY (extended)
RR
SP EU EO
26
9-12
N
AND
RX
C
A
R
54
7-7
NC
AND (character)
SS
C
A
ST D4
7-7
NI
AND
( i
mmed
i
ate)
S I C
A
ST 94
7-7
NR
AND
RR
C
R
14
7-7
0
OR
RX
C
A
R
56
7-27
OC
OR (character)
SS
C
A
ST D6
7-27
01
OR (immediate)
SI
C
A
ST
96
7-27
OR
OR
RR
C
R
16
7-27
PACK
PACK
SS
A
ST F2
7-28
RRB
RESET REFERENCE BIT
S
C
P Al
B213
10-8
RSP
RETRIEVE STATUS AND PAGE
SS
C
P A
ST D8
10-8
S
SUBTRACT
RX
C
A
IF
R
5B
7-33
SCK
SET CLOCK
S
C
P A SP
B204
10-8
SCKC
SET CLOCK COMPARATOR
S
P A SP
B206
10-9
SD
SUBTRACT NORMALIZED (long)
RX
C
A SP EU EO
LS
6B
9-14
SDR
SUBTRACT NORMALIZED (long)
RR
C
SP EU EO
LS
2B
9-14
Instructions Arranged by Mnemonic (Part 2 of 3)
B-6
IBM 4300 Processors Principles of Operation

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