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IBM 4300 Manual page 267

Processors principles of operation for ecps: vse mode
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produces the following result:
Field 1: 0000 0000 0000 0011 1001 00012
00 03 91
Field 2: 0000 0000 0001 0111 1001 00002
00 17 90
Result:
0000 0000 0001 0100 0000 00012
00 14 01
The result of this operation replaces the former
contents of field 1. Field 1 now contains the
original value of field 2.
Exclusive Or (XI)
A frequent use of the EXCLUSIVE OR (XI)
instruction is to invert a bit (change a zero bit to a
one or a one bit to a zero). For example, assume
that storage location 8082 contains 0110 1001
2 •
To invert the leftmost and rightmost bits without
affecting any of the other bits, the following
instruction can be used (assume that register 9
contains 00 00 80 80):
Machine Format
Op Code
12
97
81
Assembler Format
Op Code
Dl(Bl),12
XI
2(9),X'81'
When the instruction is executed, the byte in
storage is EXCLUSIVE ORed with the immediate
byte (the 12 field of the instruction):
Location 8082:
Immediate byte:
Result:
0110 10012
1000 00012
1110 10002
The resulting byte is stored back in location
8082. Condition code 1 is set to indicate a
nonzero result.
Notes:
1.
With the XC instruction, fields up to 256
bytes in length can be exchanged.
.
2.
With the XR instruction, the contents of two
registers can be exchanged ..
3. Because the X instruction operates storage to
register only, an exchange cannot be made
solely by the use of
x.
A-14
IBM 4300 Processors Princi.ples of Operation
4. A field EXCLUSIVE ORed with itself is
cleared to zeros.
5. For additional examples of the use of
EXCLUSIVE OR, see the section "Floating-
Point-Number Conversion" later in this
appendix.
EXECUTE (EX)
The EXECUTE instruction causes one target
instruction in main storage to be executed out of
sequence without actually branching to the target
instruction. Unless the R
1
field of the EXECUTE
instruction is zero, bits 8-15 of the target
instruction are ORed with bits 24-31 of the Rl
register before the target instruction is executed.
Thus, EXECUTE may be used to supply the length
field for an SS instruction without modifying the SS
instruction in storage. For example, assume that a
MOVE (MVC) instruction is the target that is
located at address 3820, with a format as follows:
Machine Format
D2
00
C
I
003 1 D
I
0001
Assembler Format
Op Code
Dl(L,B1),D2(B2)
MVC
3(1,12),0(13)
where register 12 contains 00 00 8913 and
register 13 contains 00 00 90 AO.
Further assume that at storage address· 5000, the
following EXECUTE instruction is located:
Machine Format
Op Code
44
o
A
I
0001
Assembler Format
Op Code
Rl,D2(X2,B2)
EX
1,0(0,10)
where register 10 contains 00 00 38 20 and register
1 contains 00 OF FO 03.

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