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floating point
(continued)
examples
A-4
register
2-2
save area for
3-11
validity bit for
11-11
shifting
(see
normalization)
format
data
decimal
8-1
floating-point
9-2
general-instruction
7-2
1/
0 instruction
12-13
information
3-2
instruction
5-2
PSW
4-4
error
6-6
fraction
9-1
frame
(see
page frame)
frame index
3-5
free-frame-capacity count (FFCC)
3-6
fullword
(see
word)
g
general instructions
7-2
data formats for
7-2
examples
A-6
general registers
2-2
alteration of (PER event)
4-12
save area for
3-10
validity bit for
11-11
guard digit
9-3
h
halfword
3-2
HALT DEVICE (HDV) instruction
12-16
HALT I/O (HIO) instruction
12-19
HALVE (HDR,HER) instructions
9-9
hexadecimal (hex) representation
5-3
i
I field of instruction
I/O (input/ output)
address
12-7
5-3
2-3, 12-2
assigned storage location for
3-10
format of
12-13
in limited channel logout
validity flags for
12-61
commands
12-35
communication area (IOCA)
control unit
2-4, 12-2
data block
12-28
device
2-4, 12-2
address
12-7
end (unit status)
error
12-13
not-ready state
status of
12-37
12-51
12-9
12-60
12-60
used for initial program loading
effect on CPU timer
4-19
effect on interval timer
4-20
error
4-24
alert (in limited channel logout)
12-61
with machine check
11-2
instructions
12-14
interface
control check -(channel status)
12-54
position (effect on interruption priority)
12-46
interface
(continued)
interruption
6-9
action
12-46
conditions
12-44
priority
12-46
logout
12-60
mask in PSW
4-4, 4-6
operations
12-2
channel compatibility
12-6
conclusion of
12-40
initiation of
12-27
storage-area designation for
12-30
termination of
12-43
selective reset
12-10
sense data
12-37
status'
12-48, 12-52
system reset
12-10
as part of program reset
4-23
system state
12-8
IC (instruction counter)
(see
instruction address)
ID
(see
channel identification, CPU identification)
ILC (instruction-length code)
6-5
IML (initial microprogram loading) controls
13-2
immediate I/O operation
12-41
immediate operand
5-3
incorrect length (channel status)
12-53
index
for address generation
5-4
instructions for handling
7-10
register
2-2
indicator
check-stop
13-2
load
13-3
manual
13-3
mode
13-4
save
13-4
test
13-5
wait
13-5
information format
3-2
initial program loading (IPL)
assigned storage locations for
effect on CPU state
4-2
initial program reset
4-23
input/output
(see
I/O)
4-24
3-10
INSERT CHARACTER (IC) instruction
7-18
INSERT CHARACTERS UNDER MASK (ICM)
instruction
7 -18
examples
A-15
INSERT PAGE BITS (IPB) instruction
10-5
INSERT PSW KEY (IPK) instruction
10-5
INSERT STORAGE KEY (ISK) instruction
10-6
instructions
address of
4-5, 4-7
validity bit for
11-12
classes of
2-2
control
10-1
damage to
11-8
decimal
8-1
examples
A-25
examples of use
A-5
execution
5-5
fetching of
5-8
access exception for
6-15
PER event
4-11
floating-point
9-1
examples
A-30
format
5-2
I/O
12-13
general
7-2
Index
X-5
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