Interval Timer - IBM 4300 Manual

enabled for external interruptions. Otherwise,
loops of external interruptions are formed.
5. The instruction STORE CPU TIMER may store
a negative value even though the CPU is
enabled for the· interruption. This is because
the CPU-timer value may be decremented one
or more times between the instants when
instruction execution is begun and when the
CPU timer is accessed. In this situation, the
interruption occurs when the execution of
STORE CPU TIMER is completed.
Interval Timer
The interval timer is a binary counter that occupies
a word at storage location 80 and has the following
format:
o
24
31
The interval timer is treated as a 32-bit signed
binary integer. In the basic form, the contents of
the interval timer are reduced by one in bit position
23 every 1/300 of a second. Higher resolution of
timing may be obtained in some models by counting
with higher frequency in one of the positions 24
through 31. In each case, the frequency is adjusted
to cause decrementing in bit position 23 at the rate
of 300 times per second. The cycle of the interval
timer is approximately 15.5 hours.
of 300 times per second. The cycle of the interval
timer is approximately 15.5 hours.
The interval timer causes an external
interruption, with bit 8 of the interruption code set
to one and bits 0-7 set to zeros. Bits 9-15 of the
interruption code are zeros unless set to ones for
another condition that is concurrently indicated.
A request for an interval-timer interruption is
generated whenever the interval-timer value is
decremented from a positive or zero number to a
negative number. The request is preserved and
remains pending in the CPU until it is cleared by
an interval-timer interruption or a program reset.
The overflow occurring as the interval-timer value
is decremented from a large negative number to a
large positive number is ignored.
The interval timer is not necessarily
synchronized with the time-of-day clock.
The interval-timer contents are updated at the
appropriate frequency whenever other machine
activity permits. The updating occurs only between
instruction executions, except that the interval
4-20 IB M 4300 Processors Principles of Operation
I
timer may be updated between units of operation of
an interruptible instruction, such as MOVE LONG.
An updated interval-timer value is normally
available at the end of each instruction execution.
When the execution of an instruction or other
machine activity causes updating to be delayed by
more than one period, the contents of the interval
timer may be reduced by more than one unit in a
single updating cycle. Interval-timer updating may
be omitted when 110 data transmission approaches
the limit of storage capability, or when a channel
sharing CPU equipment and operating in burst
mode causes CPU activity to be locked out. The
program is not alerted when omission of updating
causes the real-time count to be lost.
When the contents of the interval timer are
fetched by a channel or are used as the source of
an instruction, the result is unpredictable.
Similarly, storing by the channel at location 80
causes the contents of the interval timer to be
unpredictable.
The interval timer is not decremented when the
manual interval-timer control is set to disable. The
interval timer is also not decremented when the
CPU is not in the operating state or when the
manual rate control is set to instruction step.
Depending on the model, the interval timer may
or may not be decremented when the time-of-day
clock is in the error, stopped, or not-operational
state.
Programming Notes
1. The value of the interval timer is accessible by
fetching the word at location 80 as an operand,
provided the location is not protected against
fetching.
It
may be changed at any time by
storing a word at location 80. When location
80 is protected, any attempt by the program to
change the value of the interval timer causes a
program interruption for protection exception.
2. The value of the interval timer may be changed
without losing the real-time count by storing
the new value at locations 84-87 and then
shifting bytes 80-87 to locations 76-83 by
means of the instruction MOVE (MVC). Thus,
in a single operation, the new interval-timer
value is placed at location 80, and the old value
is made available at location 76.
If any means other than the instruction
MOVE (MVC) are used to interrogate and
then replace the value of the interval timer,