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bit. The next two instructions assemble the
modified number in an unnormalized long
floating-point format, using the left half of the
constant as the plus sign, the characteristic, and the
leading zeros of the fraction. LOAD (LD) places
the number unchanged in floating-point register 2.
The SUBTRACT NORMALIZED (SD) instruction
performs the final two steps by subtracting 2
31
in
floating-point form and normalizing the result.
Floating Point to Fixed Point
The procedure described here consists basically in
reversing the steps of the previous procedure. Two
additional considerations must be taken into
account. First: the floating-point number may not
be an exact integer. Truncating the excess
hexadecimal digits on the right requires shifting the
number one digit position farther to the right than
desired for the final result, so that the units digit
occupies the position of the guard digit Second: the
floating-point number may have to be tested as to
whether it is outside the range of numbers
representable as a signed binary integer.
Assume that floating-point register 6 contains
the number 59.25
10
=
3B.4
16
in normalized form:
FPR6
42 3B 400000000000
Further, assume three eight-byte fields in
storage: TEMP, for use as temporary storage, and
the constants 2
32
(TW032) and 2
31
(TW031R) in
the following formats:
TW032
4E 00 00 01 00 00 00 00
TW031R
4F 00 00 00 08 000000
The constant TW031R is shifted right one more
position than the constant TW031 of the previous
example, so as to force the units digit into the
guard-digit position.
The following instruction sequence performs the
integer truncation, range tests, and conversion to a
signed binary integer in general register 8 (GR8):
Result
SO
6,TW031R
FPR6:
CS 7F FF FF C5 00 00 00
BC
11,OVERFLOW
Branch to overflow
routine if result
non-negative
AW
6,TW032
FPR6:
4E 00 00 00 SO 00 00 3B
BC
4,OVERFLOW
Branch to overflow
routine if result
negative
STO 6,TEMP
TEMP:
4E 00 00 00 SO 00 00 3B
XI
TEMP+4,X ' SO '
TEMP:
4E 00 00 00 00 00 00 3B
L
S,TEMP+4
GRS:
00 00 00 03
A-32
IBM 4300 Processors Principles of Operation
The SUBTRACT NORMALIZED (SD)
instruction shifts the fraction of the number to the
right until it lines up with TW031R, which causes
the fraction digit 4 to fall to the right of the guard
digit and be lost; the result of subtracting 2
31
from
the remaining digits is renormalized. The result
should be negative; if not, the original number was
too large in the positive direction. The first
BRANCH ON CONDITION (BC) performs this
test.
The ADD UNNORMALIZED (A W) instruction
adds 232: 2
31
to correct for the previous subtraction
and another 2
31
to change to an all-positive range.
The second BC tests for a negative result, showing
that the number was too large in the negative
direction. The unnormalized result is placed in
temporary storage by the STORE (STD)
instruction. There the leftmost bit of the binary
integer is inverted by the EXCLUSIVE OR (XI)
instruction before being loaded into GR8.
Multiprogramming and Multiprocessing
Examples
Although the 4300 Processors make no provision
for multiple-CPU systems, the references to
multiprocessing may be helpful when writing
problem-state programs that are to run correctly on
multiprocessing configurations of System/370 as
well.
When two or more programs sharing common
storage locations are running concurrently in a
multiprogramming or multiprocessing environment,
one program may, for example, set a flag bit in the
common-storage area for testing by another
program.
It
should be noted that the instructions
AND (NI or NC), EXCLUSIVE OR (XI or XC),
and OR (01 or OC) could be used to set flag bits
in a multiprogramming environment; but the same
instructions may cause program logic errors in a
multiprocessing system where two or more CPUs
can fetch, modify, and store data in the same
storage locations simultaneously.
Example of a Program· Failure Using OR
Immediate
Assume that two independent programs try to set
different bits to one in a common byte in storage.
The following example shows how the use of the
instruction OR immediate (01) can fail to
accomplish this, if the programs are executed nearly
simultaneously on two different CPUs. One of the
possible error situations is depicted.
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