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IBM 4300 Manual page 305

Processors principles of operation for ecps: vse mode
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instructions
(continued)
examples
A-6
I/O
12-14
exception handling
12-27
role in I/O operations
12-5
interruptible
5-6
length code (lLC)
6-5
assigned storage locations for
3-10
for program interruptions
6-10
for supervisor-call interruption
6-19
in Be-mode PSW
4-6
length of
5-3
modification by EXECUTE instruction
7-17
prefetching of
5-9
privileged
4-5
for control
10-1
for I/O
12-14
processing damage
11-8
sequence of execution
5-1
stepping of (rate control)
13-4
effect on CPU state
4-2
effect on CPU timer
4-19
storage-control
3-6
integer
binary
7-2
address as
5-4
examples
A-2
decimal
8-2
integral boundary
3-2
interface
(see
I/O interface)
intermittent errors
11-3
internal storage
(see
storage, internal)
interrupt key
13-3
external interruption
6-8
interruptible instructions
5-6
COMPARE LOGICAL LONG
7-14
effect on interval timer
4-20
MOVE LONG
7-22
stopping of
4-2
interruption
6-1
(see also
masks)
action
I/O
12-46
machine-check
classes
6-4
code
6-4
11-5
assigned storage locations for
I/O
6-9
in BC-mode PSW
machine-check
program
6-10
supervisor-call
conditions
clearing
4-23
I/O
12-44
4-6
11-5
6-19
effect on instruction sequence
external
6-7
3-10
5-5
identification, assigned storage locations for
input/ output
6-9
machine-check
6-9, 11-5
code
11-7
masking of
6-4
pending
6-4
external
6-7
I/O
12-9
machine-check
11-5
relation to CPU state
4-2
priority
6-19
access exceptions for
6-16
X-6
IBM 4300 Processors Principfes of Operation
3-12
interruption
(continued)
external
6-8
I/O
12-46
PER event
4-10
program-interruption conditions
6-16
program
6-10
program-controlled (I/O)
12-34
restart
6-18
string
(see
string of interruptions)
supervisor-call
6-18
interval timer
4-20
damage
11-9
external interruption
6-8
manual control for
13-3
update reference
5-12
intervention required (bit in I/O-sense data)
invalid
address
CBC
6-10
11-2
in page description
11-3
in registers
11-4
in storage
11-3
channel programs
12-53
operation code
6-12
inverse move
7-22
10CA (I/O-communication area)
IPL (initial program loading)
12-60
4-24
assigned storageJocations for
k
key
access
3-7
for I/O
(see
subchannel key)
manual
(see
manual operations)
PSW
(see
PSW key)
storage
(see
storage key)
subchannel
(see
sub channel key)
key-controlled protection
3-7
exception for
6-14
I
L fields of instruction
5-3
late exception recognition
6-7
left-to-right addressing
3-1
length
field
3-2
I/O-block
12-53
(see also
count field)
instruction
5-3
register operand
5-3
3-11
variable (storage operands)
5-3
limited channel logout
12-60
assigned storage location for
3-10
link information, for BRANCH AND LINK
instruction
7-8
linkage (subroutine)
5-5
LOAD (L,LR) binary instructions
7-19
example
A-15
LOAD (LD,LDR,LE,LER) floating-point
instructions
9-10
LOAD ADDRESS (LA) instruction
7-19
examples
A-16
LOAD AND TEST (L TDR,L TER) floating-point
instructions
9-10
12-38
LOAD AND TEST (LTR) binary instruction
7-19
load-clear key
13-3

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