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Appendix B. Lists of Instructions
The following three figures list instructions
arranged by name, mnemonic, and operation code.
Some models may offer instructions that do not
appear in the figures, such as those provided for
emulation or as part of special or custom features.
The operation code 00 with a two-byte
instruction format is allocated for use by the
program when an indication of an invalid operation
is required.
It
is improbable that this operation
code will ever be assigned to an instruction
implemented in the CPU.
Explanation of Symbols in "Characteristics" and
"Op Code" Columns
A
Access exceptions.
A
1
Access exceptions; not all access
exceptions may occur; see instruction
description for details.
B
PER branch event.
C
Condition code is set.
D
Data exception.
DF
Decimal-overflow exception.
DK
Decimal-divide exception.
DM
DIAGNOSE may generate various
program exceptions and may change the
condition code.
EO
Exponent-overflow exception.
EU
Exponent-underflow exception.
EX
Execute exception.
FK
IF
II
IK
L
LS
MO
Ip
PS
PT
R
RR
RS
RX
S
SI
SO
SP
SS
ST
$
$1
*
Floating-point-divide exception.
Fixed-point-overflow exception.
Interruptible instruction.
Fixed-point-divide exception.
New condition code loaded.
Significance exception.
Monitor event.
Privileged-operation exception.
Page-state exception.
Page-transition exception.
PER general-register-alteration event.
RR instruction format.
RS instruction format.
RX instruction format.
S instruction format.
SI instruction format.
Special-operation exception.
Specification exception.
SS instruction format.
PER storage-alteration event.
Causes serialization
Causes serialization when the M
1
and R2
fields contain all ones and all zeros,
respectively.
Bits 8-14 of the operation code are
ignored.
Bits 8-15 of the operation code are
ignored.
Appendix B. Lists of Instructions
B-1
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