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CAW (channel-address word)
12-28
assigned storage location for
3-9
in initial program loading
4-24
CBC (checking-block code)
11-2
in page description
11-3
in registers
11-4
in storage
11-3
CC (chain-command) flag in CCW
12-29
CCW (channel-command word)
12-28
address in CAW
12-28
address in CSW
12-47
contents of
12-57
validity flag for
12-61
command code
12-29
in initial program loading
4-24
assigned storage locations for
3-10
prefetching of
12-30
role in I/O operations
12-5
CD (chain-data) flag in CCW
12-29
central processing unit
(see
CPU)
chain-command (CC) flag in CCW
12~29
chain-data (CD) flag in CCW
12-29
chaining
12-31
chaining check (channel status)
12-55
change bit
3-4
change recording
3-8
channel
2-4, 12-3
address
(see
I/O address)
address word (CAW)
12-28
block-multiplexer
12-4
byte-multiplexer
12-4
command word
(see
CCW)
commands
(see
commands)
control check
12-54
data check
12-54
end (I/O unit status)
12-50
equipment error
12-13
identification (ID)
12-24
assigned storage location for
3-10
in I/O-communication area
12-60
logout
12-60
masks
6-9
difference between EC and BC modes
4-3
in BC-mode PSW
4-6
model and type
12-24
multiplexer
12-4
not operational (I/O-system state)
12-9
program
12-5
programming error
12-13
selector
12-4
serialization
5-13
status
12-52
status word (CSW)
]2-47
timeout
12-4
working (I/O-system state)
12-10
channel-available interruption (CAl)
12-45
channel-to-channel adapter
12-2
characteristic (of floating-point number)
9-1
check bits
3-2, 11-1
check control
13-2
check stop
11-4
indicator
13-2
state
4-1, 11-4
due to malfunctioning manual operation
13-1
effect on CPU timer
4-19
entering of
11-4, 11-7
manual control for
13-2
checking block
11-2
code
(see
CBC)
X~2
IBM 4300 Processors Principles of Operation
checkpoint
11-2
CLEAR I/O (CLRIO) instruction
12-14
CLEAR PAGE (CLRP) instruction
10-3
clear reset
4-23
clearing of storage, by CLEAR PAGE instruction
10-3
clearing operation
by clear-reset function
4-23
by load-clear key
13-3
by system-reset-clear key
13-5
clock
(see
time-of-day clock)
clock comparator
4-18
external interruption
6-8
save area for
3-10
validity bit for
11-11
clock unit
4-18
code
checking-block
11-2
command
12-29
condition
(see
condition code)
decimal digit and sign
8-1
instruction-length
(see
instruction-length code)
interruption
6-4
monitor
6-12
operation
5-1
PER
4-10
version
10-12
commands (I/O)
12-35
chaining of
12-33
during initial program loading
4-24
code in CCW
12-29
control
12-37
read
12-36
read backward
12-36
rejection of
12-40
bit in I/O-sense data
12-38
retry of
12-39
sense
12-37
transfer in channel
12-39
write
12-36
communication area, I/O
12-60
COMPARE (C,CR) binary instructions
7-11
COMPARE (CD,CDR,CE,CER) floating-point
instructions
9-8
example
A-31
COMPARE AND SWAP (CS) instruction
7-11
examples
A-33
COMPARE DECIMAL (CP) instruction
8-5
example
A-26
COMPARE DOUBLE AND SWAP (CDS)
instruction
7 -11
COMPARE HALFWORD (CH) instruction
7-13
example
A-9
COMPARE LOGICAL (CL,CLC,CLI,CLR)
instructions
7-13
examples
A-9
COMPARE LOGICAL CHARACTERS UNDER MASK
(CLM) instruction
7-13
example
A-]O
COMPARE LOGICAL LONG (CLCL)
instruction
7 -14
example
A-I0
compa',ison
address
I
3-1
decimal
8-5
floating-point
9-8
logical
7-3
signed-binary
7-3
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