Advertisement
Register 10 contains 00 00 17 00.
Storage location 1703 contains 7E.
Execution of the instruction:
Machine Format
Op Code
'2
95
AF
A
1
003
1
Assembler Format
Op Code
01(B1),12
Cli
3(10),X ' AF '
sets condition code 1, indicating that the first
operand (the quantity in main storage) is lower
than the second (immediate) operand.
Compare Logical (CLR)
Assume that:
Register 4 contains 00 00 00 01
=
1.
Register 7 contains FF FF FF FF
=
2 32 _1.
Execution of the instruction:
Machine Format
Op Code
15
4
7
Assembler Format
Op Code
Rl,R2
ClR
4,7
sets condition code 1. Condition code 1 indicates
that the first operand is lower than the second.
If, instead, the signed-binary comparison
instruction COMPARE (CR) had been executed,
the contents of register 4 would have been
interpreted as
+
1 and the contents of register 7 as
-1.
Thus, the first operand would have been
higher, so that condition code 2 would have been
set.
COMPARE LOGICAL CHARACTERS
UNDER MASK (CLM)
The COMPARE LOGICAL CHARACTERS
UNDER MASK (CLM) instruction provides a
means of comparing bytes selected from a general
A-IO
IBM 4300 Processors Principles of Operation
register to a contiguous field of bytes in storage.
The M3 field of the CLM instruction is a four-bit
mask that selects zero to four bytes from a general
register, each mask bit corresponding, left to right,
to a register byte. In the comparison, the register
bytes corresponding to ones in the mask are treated
as a contiguous field. The operation proceeds left
to right. For example, assume that:
Three bytes starting at storage location 10200 contain FO
BC 7B
Register 12 contains 10000
Register 6 contains FO BC 5C 7B
Execution of the instruction:
Machine Format
Op Code
BO
6
o
Assembler Format
ClM
6,B ' ll0l
l
,X ' 200 ' (12)
causes the following comparison:
Register 6:
FO
Mask
1
Three bytes
starting at
location
10200
BC
1
5C
o
7B
1
Because the selected bytes are equal, condition
code 0 is set.
COMPARE LOGICAL LONG (CLCL)
The COMPARE LOGICAL LONG (CLCL)
instruction is used to compare two operands in
storage, byte by byte. Each operand can be of any
length. Two even-odd pairs of general registers
(four registers in all) are used to locate the
operands and to control the execution of the CLCL
instruction, as illustrated in the following diagram.
The first register of each pair must be an even
register, and it contains the storage address of the
byte currently being compared in each operand.
The odd register of each pair contains the length of
the operand it covers, and the leftmost byte of the
second-operand odd register contains a padding
Advertisement
Chapters
