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location is referred to as "not significant," this
value is replaced during the execution of the
instruction.
When SS-format instructions are written in the
assembler language, lengths are given as the total
number of bytes in the field. This differs from the
machine definition, in which the length field
specifies the number of bytes to be added to the
field address to obtain the address of the last byte
of the field. Thus, the machine length is one less
than the assembler-language length. The assembler
program automatically subtracts one from the
length specified when the instruction is assembled.
In some of the examples, symbolic addresses are
used in order to simplify the examples. In
assembler-language statements, a symbolic address
is represented as a mnemonic term written in all
capitals, such as FLAGS which may denote the
address of a storage location containing data or
program-control information. When symbolic
addresses are used, the assembler supplies actual
base and displacement values according to the
programmer's specifications. Therefore, the actual
values for base and displacement are not shown in
the assembler-language format or in the
machine-language format. For assembler-language
formats, in the labels that designate instruction
fields, the letter
"s"
is used to indicate the
combination of base and displacement fields for an
operand address. (For example, S 1 represents the
combination of B 1 and D 1.) In the
machine-language format, the base and
displacement address components are shown as
asterisks
(*
*
*) .
General Instructions
(See Chapter 7.)
ADD HALFWORD (AH)
The ADD HALFWORD instruction algebraically
adds the halfword contents of a storage location to
the contents of a register. The halfword storage
operand is expanded to 32 bits after it is fetched
and before it is used in the add operation. The
expansion consists in propagating the leftmost
(sign) bit 16 positions to the left. For example,
assume that the contents of storage locations
2000-2001 are to be added to register 5. Initially:
Register 5 contains 00 00 00 19
=
2510 .
Storage locations 2000-2001 contain FF FE
==
-210 .
Register 12 contains 0000 18 00.
Register 13 contains 000001 50.
A-6
13M
4300 Processors Principles of Operation
The format of the required instruction is:
Machine Format
Op Code
R1
4A
5
o
Assembler Format
Op Code
R1,02(X2,B2)
AH
5,X ' 6BO ' (13,12)
After the instruction is executed, register 5
contains 00 00 00 17
=
23
10 .
AND
(N,
NR, NI, NC)
When the Boolean operator AND is applied to two
bits, the result is one when both bits are one;
otherwise, the result is zero. When two bytes are
ANDed, each pair of bits is handled separately;
there is no connection from one bit position to
another. The following is an example of ANDing
two bytes:
First-operand byte:
Second-operand byte:
Result byte:
And (NI)
0011 01012
0101 11002
0001 01002
A frequent use of the AND instruction is to set a
particular bit to zero. For example, assume that
storage location 4891 contains 0100 0011
2 ,
To
set the rightmost bit of this byte to zero without
affecting the other bits, the following instruction
can be used (assume that register 8 contains 00 00
48 90):
Machine Format
Op Code
94
FE
Assembler Format
Op Code
01(B1),12
NI
1(S),X ' FE '
When this instruction is executed, the byte in
storage is ANDed with the immediate byte (the 12
field of the instructions):
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