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The CS instruction sets condition code 0 to
indicate a successful compare and swap, and
condition code 1 to indicate an unsuccessful
compare and swap.
The program executing the sample instructions
tests the condition code following the CS
instruction and reexecutes the flag-modifying
instructions if the CS instruction indicated an
unsuccessful comparison. When the CS instruction
is successful, the program continues execution
outside the loop and FLAGS contail}s valid data.
The branch to RETRY will be taken only if
some other program modifies the update location.
This type of a loop differs from the typical
"bit-spin" loop. In a bit-spin loop, the program
continues to loop until the bit changes. In this
example, the program continues to loop only if the
value does change during each iteration.
If
a
number of CPUs simultaneously attempt to modify
a single location by using the sample instruction
sequence, one CPU will fall through on· the first
try, another will loop once, and so on until all
CPUs have succeeded.
Updating Counters
In this example, a 32-bit counter is updated by a
program using the CS instruction to ensure that the
counter will be correctly updated. The original
value of the counter is obtained by loading the
word containing the counter into general register 7.
This value is moved into general register 8 to
provide a modifiable copy, and general register 6
(containing an increment to the counter) is added
to the modifiable copy to provide the updated
counter value. The CS instruction is used to ensure
valid storing of the counter.
The program updating the counter checks the
result by examining the condition code. The
condition code 0 indicates a successful update, and
the program can proceed.
If
the counter had been
changed between the time that the program loaded
its original value and the time that it executed the
CS instruction, the CS instruction would have
A-34
IBM 4300 Processors Principles of Operation
loaded the new counter value into general register
7 and set the condition code to 1, indicating an
unsuccessful update. The program then must
update the new counter value in general register 7
and retry the CS instruction, retesting the condition
code, and retrying until a successful update is
completed.
The following instruction sequence performs the
above procedure:
LA
6, 1
Put increment
(1)
into
GR6
L
7,CNTR
Put original counter
value into GR7
LOOP LR
8,7
Set up copy in GR8 to
modify
AR
8,6
Increment copy
CS
7,8,CNTR Update counter in
storage
BC
4,LOOP
If original value had
changed, update new
value
The following shows two CPU s, A and B,
executing this instruction sequence simultaneously:
both CPUs attempt to add one to CNTR.
CPU A
CPU B
Comments
GR7 GR8
CNTR
GR7 GR8
- -
16
16 16
CPU A loads GR7
and GR8 from CNTR
16
16
CPU B loads GR7
and GR8 from CNTR
17
CPU B adds one to
GR8
17
CPU A adds one to
GR8
17
CPU A executes CS;
successful match,
store
17
CPU B executes CS;
no match, GR7
changed to CNTR
value
18
CPU B loads GR8
from GR7, adds
one to GR8
18
CPU B executes CS;
successful match,
store
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