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BeT
[RX]
146 1
o
8
12
16
20
31
A one is subtracted from the first operand, and the
result is placed in the first-operand location. The
first operand and result are treated as 32-bit binary
integers, with overflow ignored. When the result is
zero, normal instruction sequencing proceeds with
the updated instruction address. When the result is
not zero, the instruction address in the current
PSW is replaced by the branch address.
In the RX format, the second-operand address is
used as the branch address. In the RR format, the
contents of bit positions 8-31 of the general
register specified by R
z
are used as the branch
address; however, when the R
z
field contains zeros,
the operation is performed without branching.
The branch address is computed before the
counting operation.
Condition Code: The code remains unchanged.
Program Exceptions: None.
Programming Notes
1. An example of the use of BRANCH ON
COUNT is given in Appendix A.
2. The first operand and result can be considered
as either signed or unsigned binary integers
since the result of a binary subtraction is the
same in both cases.
3. An initial count of one results in zero, and no
br~nching
takes place; an initial count of zero
results in -1 and causes branching to be
executed; an initial count of -1 results in -2
and causes branching to be executed; and so
on. In a loop, branching takes place each time
the instruction is executed until the result is
again zero. Note that, because of the number
range, an initial count of _2 31 results in a
positive value of 2 31 - 1.
4. Counting is performed without branching when
the R
z
field in the RR format contains zero.
BRANCH ON INDEX HIGH
o
8
12
16
20
31
7-10
IBM 4300 Processors Principles of Operation
BRANCH ON INDEX LOW OR EQUAL
BXLE
R1,R3,D2(B2)
[RS]
o
8
12
16
20
31
An increment is added to the first operand, and the
sum is compared with a compare value. The result
of the comparison determines whether branching
occurs. Subsequently, the sum is placed in the
first-operand location. The second-operand
address is used as a branch address. The R3 field
designates registers containing the increment and
the compare value.
For BXH-
j ,
when the sum is high, the instruction
address in the current PSW is replaced by the
branch address. When the sum is low or equal,
normal instruction sequencing proceeds with the
updated instruction address.
For BXLE, when the sum is low or equal, the
instruction address in the current PSW is replaced
by the branch address. When the sum is high,
normal instruction sequencing proceeds with the
updated instruction address.
When the R3 field is even, it designates a pair of
registers; the contents of the even and odd registers
of the pair are used as the increment and the
compare value, respectively. When the R3 field is
odd, it designates a single register
~Jhe
contents of
which are used as both the increment and the
compare value.
For purposes of the addition and comparison, all
operands and results are treated as 32-bit signed
binary integers. Overflow caused by the addition is
ignored.
The original contents of the _ compare-value
register are used as the compare value even when
that register is also specified to be the first-operand
location. The branch address is computed before
the addition and comp-arison.
/
The sum is placed in the first-operand location,
regardless of whether the branch is taken.
Condition Code: The code remains unchanged.
Program Exceptions: None.
Programming Notes
1.
An example of the use of BRANCH ON
INDEX HIGH is given in Appendix A.
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