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xc
[SS]
r------.------~--~-/--~--~-/
' - - - - _ I
D_7
_ I
-l..-_ _
L
_LI
_B
1---L1_~ 1
B 2
~~
o
8
16
20
32
36
47
The EXCLUSIVE OR of the first and second
operands is placed in the first-operand location.
The connective EXCLUSIVE OR is applied to
the operands bit by bit. A bit position in the result
is set to one if the corresponding bit positions in
the two operands are unlike; otherwise, the result
bit is set to zero.
For XC, each operand is processed left to right.
When the operands overlap, the result is obtained
as if the operands were processed one byte at a
time and each result byte were stored immediately
after the necessary operand byte is fetched.
For XI, the first operand is one byte in length,
and only one byte is stored.
Resulting Condition Code:
o
Result is zero
1
Result is not zero
2
3
Program Exceptions:
Access (fetch, operand 2, X and XC; fetch and
store, operand 1, XI and XC)
Programming Notes
1. An example of the use of EXCLUSIVE OR is
given in Appendix A.
2. The instruction EXCLUSIVE OR may be used
to invert a bit, an operation particularly useful
in testing and setting programmed binary bit
switches.
3. A field EXCLUSIVE-ORed with itself becomes
all zeros.
4. For XR, the sequence A EXCLUSIVE-OR B B
EXCLUSIVE-OR A, A EXCLUSIVE-OR B '
results in the exchange of the contents of A
and B without the use of an additional general
register.
5. Accesses to the first operand of XI and XC
consist in fetching a first-operand byte from
storage and subsequently storing the updated
value. These fetch and store accesses to a
particular byte do not necessarily occur one
immediately after the other. Thus, the
instruction EXCLUSIVE OR cannot be safely
used to update a location in storage if the
possibility exists that another CPU or a channel
may also be updating the location. An example
of this effect is shown for the instruction OR
(01)
in the section "Multiprogramming and
Multiprocessing Examples" in Appendix A.
EXECUTE
144
1
I
R 1
I
X2
I
B2
D2
o
8
12
16
20
31
The single instruction at the second-operand
address is modified by the contents of the general
register specified by R 1 , and the resulting target
instruction is executed.
When the R 1 field is not zero, bits 8-15 of the
instruction designated by the second-operand
address are ORed with bits 24-31 of the register
specified by R
l'
The
~Ring
does not change either
the contents of the register specified by R1 or the
instruction in storage, and it is effective only for
the interpretation of the instruction to be executed.
When the R1 field is zero, no ORing takes place.
The target instruction may be two, four, or six
bytes in length. The execution and exception
handling of the target instruction are exactly as if
the target instruction were obtained in normal
sequential operation, except for the instruction
address and the instruction -length code.
The instruction address of the current PSW is
increased by the length of EXECUTE. This
updated address and the instruction-length code of
EXECUTE are used, for example, as part of the
link information when the target instruction is
BRANCH AND LINK. When the target
instruction is a successful branching instruction, the
instruction address of the current PSW is replaced
by the branch address specified by the target
instruction.
When the target instruction is in turn an
EXECUTE, an execute exception is recognized.
The effective address of EXECUTE must be
even; otherwise, a specification exception is
recognized. When the target instruction is two or
three halfwords in length but can be executed
without fetching its second or third halfword, it is
unpredictable whether access exceptions are
recognized for the unused halfwords. Access
exceptions are not recognized for the
second-operand address when the address is odd.
Chapter 7. General Instructions
7 -17
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