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Another control provides at least two settings to
specify the action, if· any, to be taken when the
address match occurs. The two settings are normal
and stop. When this control is set to stop, the test
indicator is turned on.
1. The normal setting disables the address-
compare operation.
2. The stop setting causes the CPU to enter the
stopped state on an address match. Depending
on the model and the type of reference,
pending I/O, external, and machine-check
interruptions mayor may not be taken before
entering the stopped state.
A third control may specify the type of storage
reference for which the address comparison is to be
made. A model may provide one or more of the
following settings, as well as others:
1. The any setting causes the address comparison
to be performed on all storage references.
2. The data-store setting causes address
comparison to be performed when storage is
addressed to store data.
3. The I/O setting causes address comparison to
be performed when storage is addressed by a
channel to transfer data or to fetch a
channel-command word. Whether references
to the channel-address word or the
channel-status word cause a match to be
indicated depends on the model.
I
4. The instruction-address setting causes address
comparison to be performed when storage is
addressed to fetch an instruction. The
rightmost bit of the address setting mayor may
not be ignored. The match is indicated only
when the first byte of the instruction is fetched
from the selected location. It depends on the
model whether a match is indicated when
fetching the target instruction of EXECUTE.
Alter-and-Display Controls
The operator facilities provide controls and
procedures to permit the operator to alter and
display the contents of addressable locations in
storage, the storage keys, the page bits, the general,
floating-point, and control registers, and the PSW.
Information in storage can only be altered or
displayed if the storage pages containing the
information are in the connected or addressable
state.
Before alter-and-display operations may be
performed, the CPU must first be placed in the
stopped state. During alter-and-display operations,
13-2
IBM 4300 Processors Principles of Operation
the manual indicator may be turned off
temporarily, and the start and restart keys may be
inoperative.
Check Control
The check control has at least two settings, stop
and normal. If the control is set to stop, the CPU
enters the check-stop state when either:
1. A machine-check condition is detected and not
corrected
2. A channel check occurs which would cause
information to be stored in a channel-logout
area at locations 176-179
Whether information is actually stored in
assigned storage locations as a result of the
machine check or channel check, the indications
given for the cause of the stop, and the manner of
resuming CPU operation depend on the model.
If the check control is set to normal, the action
resulting from the detection of a machine check or
channel check is the same as described in Chapter
11, "Machine-Check Handling," or in Chapter 12,
"Input/ Output Operations," respectively.
The test indicator is on while the check control
is set to stop.
Programming Note
Except that recovery from a machine check or a
channel check with logout is not possible, the check
control permits a System/360 program, which uses
assigned storage locations above 128 as ordinary
storage, to be run in the BC mode.
Check-Stop Indifator
The check-stop indicator is on when the CPU is in
the check-stop state. Reset operations normally
cause the CPU to leave the check-stop state and
thus turn off the indicator. The manual indicator
may also be on in the check-stop state.
IML Controls
The IML controls perform initial microprogram
loading (IML). The IML operation selects the
ECPS:VSE architectural mode or the System/370
architectural mode of operation.
When the IML operation is completed, the state
of the affected CPU, channels, storage, and
operator facilities is the same as if a power-on reset
had been performed, except that the value and
state of the time-of-day clock are not reset.
The IML controls are effective while the power
is on.
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