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designated by the R2 field is inserted in the general
register designated by the Rl field.
Bits 8-20 of the register designated by the R2
field designate the page. Bits 0-7 and 21-27 of the
register are ignored. Bits 28-31 of the regi~ter
must be zeros; otherwise, a specification exception
is recognized, and the operation is suppressed.
The execution of the instruction depends on
whether the PSW specifies the BC or BC mode. In
the EC mode, the seven-bit storage key is inserted
in bit positions 24-30 of the register designated by
the Rl field, and bit3
f
is set to zero. In the BC
mode, bits 0-4 of the storage key are placed in bit
positions 24-28 of that register, and bits 29-31 of
the register are set to zeros. In both modes, the
contents of bit positions 0-23 of the register remain
unchanged.
The reference to the storage key is not subject to
a protection exception. The storage key can be
accessed regardless of the state of the addressed
page.
Condition Code: The code remains unchanged.
Program Exceptions:
Addressing (operand 2)
Privileged Operation
Specification
LOAD CONTROL
o
8
12
16
20
31
The set of control registers starting with the control
register designated by the R
1
field and ending with
the control register designated by the R3 field is
loaded from the locations designated by the
second-operand address.
The storage area from which the contents of the
control registers are obtained starts at the location
designated by the second-operand address and
continues through as many storage words as the
number of control registers specified. The control
registers are loaded in ascending order of their
addresses, starting with the control register
designated by the R
1
field and continuing up to
and including the control register designated by the
R3
field, with control register 0 following control
register 15. The second operand remains
unchanged.
10-6
IBM 4300 Processors Principles of Operation
The second operand must be designated on a
word boundary; otherwise, a specification exception
is recognized, and the operation is suppressed.
Condition Code: The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2)
Privileged Operation
Specification
Programming Note
To ensure that existing programs run if and when
new facilities using additional control-register
positions are defined, only zeros should be loaded
in unassigned control-register positions.
LOAD FRAME INDEX
o
8
12
16
20
31
The frame index of the page frame that is
connected to the storage page designated by the
second-operand addressjs returned in the general
register designated by the R
1
field.
Bits 8-20 of the second-operand address
designate the page. Bits 0-7 and 21-31 of the
address are ignored. Bits 12-15 of the instruction
are ignored.
The frame index is an unsigned binary integer.
It
is right-aligned in the R
1
register, and the
remaining high-order bits of the register are set to
zeros. The frame index is unique and may have
any value from zero to EFCC - 1, where EFCC is
the existing-frame-capacity count.
The frame index is returned only when the page
is connected or addressable. When the page is
disconnected or not provided (condition codes 2 or
3), the R
1
register remains unchanged.
Condition code 0, 1, or 2 is set when the page is
addressable, connected, or disconnected,
respectively. Condition code 3 is set when the
address is invalid, that is, the value of bits 8-20 of
the second-operand address equals or exceeds the
page-capacity count.
Resulting Condition Code:
o
Index returned, page is addressable
1
Index returned, page is connected
2
Index not returned, page is disconnected
3
Index not returned, address is invalid
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