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byte which is used to extend the shorter operand, if
any, to the same length as the longer operand.
The following illustrates the assignment of
registers:
R1(even)
1lllllllllFirst-Operand
Address
o
8
31
R1+
1
(odd)
I11111111I
First-Operand Length!
o
8
31
R2(even)
!11111111!Second-Operand
Addressl
o
8
31
R2+ 1 (odd) Ipad Byte/Second-operand Length I
o
8
31
Since the CLCL instruction may be interrupted
during execution, the interrupting program must
preserve the contents of the four registers for use
when the instruction is resumed.
The following instructions set up two register
pairs to control a text-string comparison. For
example, assume:
Operand 1
Address: 20800 (hex)
Length:
100 (dec)
Operand 2
Address: 20AOO (hex)
Length:
132 (dec)
Padding Byte
Address: 20003 (hex)
Length:
1
Value:
40 (hex)
Register 12 contains 00 02 00 00
The setup instructions are:
LA
4,X'800'(12)
Point register 4 to start of first
operand
LA
5, 100
Set register 5 to length of first
operand
LA
8,X'AOO'(12)
Point register 8 to start of second
operand
LA
9,132
Set register 9 to length of second
operand
IeM 9,B' 1000' ,3(12)
Insert padding byte in leftmost
byte position of register 9.
Register pair 4,5 defines the first operand. Bits
8-31 of register 4 contain the storage address of
the start of an EBCDIC text string, and bits 8-31
of register 5 contain the length of the string, in this
case 100 bytes.
Register pair 8,9 defines the second operand,
with bits 8-31 of register 8 containing the starting
location of the second operand and bits 8-31 of
register 9 containing the length of the second
operand, in this case 132 bytes. Bits 0-7 of register
9 contain an EBCDIC blank character (X'40') to
pad the shorter operand.
In this example, the
padding byte is used in the first operand, after the
100th byte, to compare with the remaining bytes in
the second operand.
With the register pairs thus set up, the format of
the CLCL instruction is:
Machine Format
Op Code
R1
R2
OF
4
8
Assembler Format
Op Code
Rl,R2
CLCL
4,8
When this instruction is executed, the
comparison starts at the left end of each operand
and proceeds to the right. The operation ends as
soon as an inequality is detected or the end of the
longer operand is reached.
If
this CLCL instruction is interrupted after 60
bytes have compared equal, the operand lengths in
registers 5 and 9 will have been decremented to
X'28' and X'48', respectively, and the operand
addresses in registers 4 and 8 will have been
incremented to X'2083C' and X'20A3C'. The
padding byte X'40' remains in register 9. When
the CLCL instruction is reissued with these register
contents, the comparison resumes at the point of
interruption.
Now, assume that the instruction is interrupted
after 110 bytes. That is, the first 100 bytes of the
second operand have compared equal to the first
operand, and the next 10 bytes of the second
operand have compared equal to the padding byte
(blank). The residual operand lengths in registers
5 and 9 are 0 and X' 16', respectively, and the
operand addresses in registers 4 and 8 are X'20864'
Appendix A. Number Representation and Instruction-Use Examples
A-11
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